Choose an option from the left upper box
Navigate to an item for the selected option in the left lower box
Repeat after completing chosen activity - in this box

  Submission of grades [Jun 09, 2020. 16:43:33]

All your marks have been uploaded to WBCM for generating the grades, to be send in a day or two.

---

  ASM charts [Apr 20, 2020. 09:58:25]

Notes on ASM charts have been uploaded; these help to specify the behaviour of a controller FSM in the form of a flowchart

---

  Burst mode design [Apr 11, 2020. 03:33:15]

M/c optimisation and state assignment for burst mode design

---

  State encoding [Apr 07, 2020. 01:49:22]

State encoding for asynchronous m/c design

---

  Asynchronous circuit synthesis [Apr 06, 2020. 06:56:41]

Synthesis of SIC fundamental-mode asynchronous circuits

Lectures in three parts (from other section): part 1, part 2, part 3

---

  Logic minimisation to handle hazards [Apr 02, 2020. 03:16:30]

Basic notions of hazards is introduced with examples and 2-level hazard free logic minimisation

Lectures in three parts (from other section): part 1, part 2, part 3

---

  FSM optimisation [Mar 20, 2020. 10:37:50]

The minimisation procedure of an incompletely specified FSM has been illustrated for $M_E$. Please work out the procedure for $M_D$. Any problem faced can be posted in the WhatsApp group for clarification.

---

  Wed, Mar 11, 2020 [Mar 11, 2020. 06:27:21]

Iterative networks, inability of FSM to multiply arbitrarily large numbers, k-equivalence, minimisation of a completely specified FSM

---

  Thu, Mar 05, 2020 [Mar 10, 2020. 23:22:43]

Working of synchronous up/down counters; derivation of excitation for flip flops -- JK, T; assignment to design a up counter using D flip flops

---

  Wed, Mar 04, 2020 [Mar 04, 2020. 15:59:49]

Shift register with parallel load, left/right shift/rotate; barrel shifter

---

  Mon, Mar 02, 2020 [Mar 02, 2020. 09:43:10]

Common sequential circuits: shift registers, counters

---

  Thu, Feb 27, 2020 [Mar 02, 2020. 09:42:04]

Mealy and Moore m/cs (contd.)

---

  Wed, Feb 26, 2020 [Feb 23, 2020. 17:23:21]

Mealy and Moore m/cs

---

  Midsem announcement [Feb 17, 2020. 22:25:41]

Date:

2019, Feb 19, Wed

Time:

9am – 11am

Venue:

F116, F142, NR113, NR114, NR412

Syllabus:

Except for latches and flip flops, everything covered until the midsems

Instructions:

Calculators are not permitted; carry pencil(s) and eraser

QP:

Questions and solutions

---

  Thu, Feb 13, 2020 [Feb 13, 2020. 09:36:05]

Latches and flip flops

---

  Wed, Feb 12, 2020 [Feb 13, 2020. 09:35:00]

BCLA delay computation, comparator design with lookahead, other combinational circuits

---

  Mon, Feb 10, 2020 [Feb 10, 2020. 07:14:58]

Parallel parity bit generator, decoder, serial to parallel converter, comparators, data selectors / multiplexers, priority encoders

---

  Thu, Feb 06, 2020 [Feb 06, 2020. 09:47:06]

Adder design

---

  Wed, Feb 05, 2020 [Feb 06, 2020. 00:18:24]

Covering table reduction by essential cube/product, row dominance, column dominance; identification of the cyclic core; branch and bound (with recursive covering); Petrick's method to generate all possible solutions (especially for the cyclic core)

---

  Mon, Feb 03, 2020 [Feb 03, 2020. 09:45:29]

Introduction to 2-level Boolean function optimisation using the Quine-McCluskey method

---

  Thu, Jan 30, 2020 [Feb 03, 2020. 09:44:13]

More examples of Karnaugh maps

---

  Mon, Jan 27, 2020 [Jan 27, 2020. 03:06:08]

Shannon decomposition, introduction to Boolean function optimisation using Karnaugh maps

---

  Thu, Jan 23, 2020 [Jan 23, 2020. 09:16:13]

Properties of XOR, series-parallel networks, gate networks

---

  Wed, Jan 22, 2020 [Jan 23, 2020. 09:14:16]

Hamming distance, error correction, error detection, number of bits needed, cannonical expressions, number of Boolean functions

---

  Class test 1 announcement [Jan 20, 2020. 16:16:00]

Date:

2019, Feb 05, Wed

Time:

6:15pm – 7:15pm

Venue:

CSE-107 (sec-1), CSE-108 (sec-1), CSE-119 (sec-2), CSE-120 (sec-2), CSE-302 (overflow)

Syllabus:

Number systems, weighted codes, BCD code, Gray code, excess-3 code, single error detection (parity, 2-out-of-5), conversion between number systems/codes, representation of signed (±) numbers, single error correction (Hamming code), switching algebra, identities (associativity, idempotence, absorption, boundedness, involution, DeMorgan's laws)

Instructions:

Calculators are not permitted; carry pencil(s) and eraser

QP:

Questions and solutions

---

  Mon, Jan 20, 2020 [Jan 18, 2020. 09:18:59]

Boolean lattice representation and Boolean algebra from a Boolean lattice, switching expressions

---

  Thu, Jan 16, 2020 [Jan 16, 2020. 09:39:27]

More on POs and lattices

---

  Wed, Jan 15, 2020 [Jan 15, 2020. 07:52:37]

Binary codes (contd.), sets, relations, POs and lattices

---

  Mon, Jan 13, 2020 [Jan 13, 2020. 09:24:35]

Binary codes (contd.)

---

  Thu, Jan 09, 2020 [Jan 09, 2020. 09:09:34]

Handling numbers

---

  Wed, Jan 08, 2020 [Jan 08, 2020. 08:06:20]

Handling numbers

---

  Mon, Jan 06, 2020 [Jan 06, 2020. 08:54:49]

Introductory topics

---

  Thu, Jan 02, 2020 [Jan 02, 2020. 00:41:51]

Course introduction

---

  COs [Jan 02, 2020. 00:32:25]

• Representation of information in Boolean form, including number systems
• Design and optimisation of combinational circuits
• Design and optimisation of synchronous sequential circuits
• Design and optimisation of asynchronous sequential circuits
• Design and operation of common digital building blocks

---

  Class schedule [Jan 02, 2020. 00:24:05]

Venue:

NC-234 / NC-231

Monday:

10am -- 10:55am

Wednesday:

8am -- 9:55am

Thursday:

10am -- 10:55am

---

  Books and References [Jan 02, 2020. 00:22:05]

1. M. Morris Mano and Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th Edition, Pearson Education, 2013.
2. Zvi Kohavi and Niraj K. Jha, Swithcing and Finite Automata Theory, 3rd Edition, Cambridge University Press, 2010.
3. Randy H. Katz and Gaetano Borriello, Contemporary Logic Design, 2nd Edition, Pearson Education, 2005.
4. Joseph Cavanagh, Digital Design and Verilog HDL Fundamentals, CRC Press, 2008.
5. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Sunsoft Press, 1996.
6. Douglas J. Smith, HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs & FPGAs Using VHDL or Verilog, Doone Publications, 1998.
7. http://www.asic-world.com/
8. Jacob Millman and Herbert Taub, Pulse, Digital and Switching Waveforms, 3rd Edition, Tata McGraw-Hill, 2011.
9. Herbert Taub and Donald L. Schilling, Digital Integrated Circuits, Tata McGraw-Hill, 2008.

---

  Course syllabus [Jan 02, 2020. 00:20:45]

CS21002 Switching Circuits and Logic Design

L-T-P: 3-1-0, Credit: 4

• Introduction: Logic design, transistors as switches, CMOS gates, sequential circuits, some examples.
• Digital Systems: Representation of numbers, binary codes, Gray code, error-detecting and error-correcting codes, registers, binary logic, basic logic gates.
• Boolean Algebra: Boolean operations, Boolean functions, algebraic manipulations, minterms and maxterms, sum-of-products and product-of-sum representations, two-input logic gates, functional completeness.
• Minimization of Boolean Functions: Karnaugh map, don't-care conditions, prime implicants, Quine–McCluskey technique, NAND/NOR circuits, introduction to Verilog.
• Combinational Circuits: Adder, subtractor, multiplier, comparator, decoders, encoders, multiplexers, demultiplexers, Verilog models of combinational circuits.
• Synchronous Sequential Circuits: Finite-state machines, latches and flip-flops (SR, D, JK, T), synthesis of clocked sequential circuits, Mealy and Moore machines, state minimization, Verilog models of sequential circuits.
• Registers and Counters: Registers and shift registers, sequential adders, binary and BCD ripple counters, synchronous counters
• Algorithmic State Machines: ASM charts, ASM blocks, controller and data-path design
• Asynchronous Sequential Circuits: Analysis and synthesis, static and dynamic hazards, elimination of hazards

---