State assignment for asynchronous m/c design

Setup

Original flow graph

G sA A sA->sA 00,01 sD D sA->sD 10,11 sB B sB->sA 01 sB->sB 00,10 sC C sB->sC 11 sC->sA 00 sC->sB 10 sC->sC 0,1 sD->sB 00 sD->sC 01 sD->sD 10,11

Flow graph after state encoding with 2 bits

G sA A (00) sA->sA 00,01 sD D (10) sA->sD 10,11 sB B (01) sB->sA 01 sB->sB 00,10 sC C (11) sB->sC 11 sC->sA 00 sC->sB 10 sC->sC 01,11 sD->sB 00 sD->sC 01 sD->sD 10,11

Flow graph after state encoding with 3 bits

G sA A (000) sA->sA 00,01 sD D (110) sA->sD 10,11 sB B (001) sB->sA 01 sB->sB 00,10 sC C (011) sB->sC 11 sC->sA 00 sC->sB 10 sC->sC 01,11 sD->sB 00 sD->sC 01 sD->sD 10,11

Flow graph after state encoding with 3 bits and extra states

G sA A (000) sA->sA 00,01 sE E (010) sA->sE 10,11 sB B (001) sB->sA 01 sB->sB 00,10 sC C (011) sB->sC 11 sC->sB 10 sC->sC 01,11 sC->sE 00 sD D (110) sD->sD 10,11 sF F (111) sD->sF 00,01 sE->sA 00 sE->sD 10,11 sF->sC 01 sG G (101) sF->sG 00 sG->sB 00

Questions

Exercise