Power-aware Proportionally Fair hard-realtime scheduler(Ongoing since Nov 2012) [PROJECT] [PAPER] [CODE] (Guidance: Dr. Arnab Sarkar, Dept. of Computer Science and Engineering, IIT Guwahati)
We are currently working on designing a ERFair scheduler with provision for processor shutdown, in muliprocessor systems
We use the idea of stealing slack, accumulated in ERFair systems and greedily try to shutdown processors, to maximize the shutdown length
The second part of the project involves implementing DVS (Dynamic Voltage Scheduling) to power down the processors, while conserving schedulability
Finally we aim to study the efficacy of using processor shutdown with DVS technology.
Developing a standard realtime systems scheduler(Ongoing since Dec 2012) [ CODE] (Independent Project)
The project aims to develop a realtime systems simulator, to provide a standard platform for simulations (similar to lines of ns2).
The project has been started very recently. Once a basic structure and design is available, I will provide a GitHub link.
Project aimed at developing a scheduler for hard realtime systems, which could minimize the number of task migrations by being aware of the task processor affinity and partition oriented schemes.
Studied the effect of using partition oriented scheme on ERFair algorithms, like ERFair and Sticky ERFair.
Designed a partition heuristic, to be used with Sticky ERFair algorithm for tremendously reducing the task migrations among processors
The paper has been submitted to IEEE Transactions on Computers. You can have a look at the paper here
Multicasting in Delay Tolerant Networks(May 2010 - April 2011) [PROJECT] [PAPER][THESIS] [CODE] (Guide: Prof. Arobinda Gupta, IIT Kharagpur, Bachelor's Thesis Project)
We tried to address the problem of space utilization on nodes, in a DTN tree-based multicasts.
Store and Forward Mechanism, results in storing of messages in intermediate nodes.
We developend a tree computation algorithm, which produced a "thinner" and "deeper" tree, with lesser number of nodes
We studied the efficacy of the algorithm on generated SLAW mobility traces.
The work has been submitted in International Journal of Computing and Network Technology. You can have a look at the paper here
Gender Prediction of Indian Names (July - Nov 2010) [PROJECT] [PAPER] (Independent Project with Manaal Faruqui)
The project aims at idetifying features in the first names of indian origin, that characterizes the geneder of the person.
We made a corpus of indian names, from websites showinf baby names for boy/girl child.
We figured out many probable features like: vowel ending in a name (mostly for female), sonorance ...
We used various machine learing algorithms to train classifiers. Finally figured out SVM gave best results for a particular set of features.
We present the work as a paper in IEEE Students' Technology Symposium, 2011. You can download the paper here.
Parallel Group Mining Algorithms (May 2011 - Mar 2012) [THESIS] (Guide: Prof. Arobinda Gupta, IIT Kharagpur, Master's Thesis Project)
The Project aimed at designing a way to run group minning algorithms, on a small hadoop cluster.
We studied the structure of the data on which the group mining algorithms execute.
Wrote a master-worker scheduler to schedule, partial AI searches in computers in a cluster, while leveraging Hadoop.
We ran several experiments on the efficacy of the algorithm, for different data sets, data formats and size of hadoop cluster
Spectral Analysis of Social Networks (July 2011 - Dec 2011) [PPT] [CODE] (Guide: Prof. Niloy Ganguly)
The project involved computing metrics on real-world networks like facebook, twitter and Autonomous router networks .. etc
We created crawlers for Facebook and twitter network. The code can be found here
We studied several charecteristic properties of the graphs, like Eigen vectors, Centralities, Degree distributions ... etc
We ran simulations of Node removal attacks on these networks to study the resilience characteristics.
We also did these simulation studies for bi-modal graphs
Scan-Chain Reordering to reduce testing power (Jan 2012 - Mar 2012) [REPORT] [CODE] (VLSI laboratory, Prof. Indranil Sen Gupta)
The project aimed at studing the efficacy of machine learning algorithms on scan-chain re-ordering in VLSI circuits to reduce the power consumption for given set of test vectors
We modeled the problem as a TSP and studied the efficacy of simualted annealing process on the reduction of test power.
We tested the process on ISCAS89 benchmark circuits and showed a reduction of around 30% in the power consumption.
Matching of Orthogonal Polygons (July 2008 - Aug 2008) [PROJECT] [CODE] (Guide: Prof. Partha Bhowmick, IIT Kharagpur)
The Project aimed at designing heuristic algorithms for inexact matching of orthogonal polygons.
Our first step was to generate random orthogonal polygons and create a database agaist which query shall be done.
We implemented Inflate-and-cut algorithm for polygon generation.
We figured out a method of encoding the polygon, so that it reamins same under rotation. We then made some heuristic algorithms to find an inexact match of query polygons agaist the data base and retun best matches