Design of Registers and Counters :
In a sequential circuit the present output is determined by both the present input and the past output. In order to receive the past output some kind of memory element can be used. The memory element commonly used in the sequential circuits are time-delay devices. The block diagram of the sequential circuit-
A circuit with flip-flops is considered a sequential circuit even in the absence of combinational logic. Circuits that include flip-flops are usually classified by the function they perform. Two such circuits are registers and counters:
- Register is a group of flip-flops. Its basic function is to hold information within a digital system so as to make it available to the logic units during the computing process.
- Counter is essentially a register that goes through a predetermined sequence of states.
There are various different kind of Flip-Flops. Some of the common flip-flops are: R-S Flip-Flop, D Flip-Flop, J-K Flip-Flop, T Flip-Flop. The block diagram of different flip-flops are shown here -
Types of Registers:
4-bit Parallel-in Parallel-out
Types of Counters:
4-bit Synchronous Binary Counter
4-bit Synchronous Ring Counter
4-bit Synchronous Johnson Counter
Design Issues :
The four different types of flip-flops are supplied here. One can easily build any register or counter using those flip-flop and different logic gates. But the clock input is under development, so it is not possible now to build any register or counter completely.
4-bit Serial-in Serial-out:
4 bit serial-in serial-out register accepts digital data serially that is one bit at the time on one line. It produces the stored information on its output also in serial form. This is a shift register, as The binary number is "Shifted" one bit at time from one flip flop to the next. The block diagram is-
4-bit Serial-in Parallel-out:
In serial-in parallel-out register the data are loaded serially and read out in parallel. The block diagram is-
4-bit Parallel-in Serial-out:
In parallel-in serial out register the bits are entered simultaneously into their respective stages on parallel-lines, rather than on a bit-by-bit basis on one line as with serial data inputs and output is read out out parallaly. The block diagram is-
4-bit Parallel-in Parallel-out:
In parallel-in parallel out register the data is loaded in parallel and shifted out serially. The block diagram is-
4-bit Synchronous Binary Counter:
A counter is a sequential circuit that moves through a predefined sequence of states upon applying of clock pulses. The sequence of states may follow the binary number sequence or an arbitrary manner (no sequence). The simplest example of a counter is the binary counter which follows the binary number sequence. An n-bit binary counter contains n flip-flops and can count binary numbers from 0 to (2n -1)(up counter which is incremental, if it counts decrementally it is then down counter). logic diagram of 4 bit synchronous counter-
4-bit Synchronous Ring Counter:
If the output of a shift register is fed back to the input. a ring counter results. The data pattern contained within the shift register will recirculate as long as clock pulses are applied. logic diagram of synchronous ring counter-
Timing diagram:
4-bit Synchronous Johnson Counter:
If the complement output of a ring counter is fed back to the input instead of the true output, a Johnson counter results. This "reversed" feedback connection has a profound effect upon the behavior of the otherwise similar circuits. Recirculating a single 1 around a ring counter divides the input clock by a factor equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice the number of stages. logic diagram of synchronous Johnson counter-
Timing Diagram-
Design of Registers and Counters :
Basic stage
Multiple choice questions:
- Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
- Ring counter is similar to
- what is the number of flipflops needed to design a mod-19 counter?
- The dynamic problem hazards can occur both in combinational and sequential circuits
- How is a J-K flip-flop made to toggle?
The Q output is ALWAYS identical to the CLK input if the D input is HIGH
The logic level at the D input is transferred to Q on NGT of CLK
The Q output is ALWAYS identical to the D input when CLK = PGT
The Q output is ALWAYS identical to the D input
Stepping switch
latch
SR flipflop
Toggle flipflop
5
4
6
7
True
False
J = 0, K = 0
J = 1, K = 1
J = 1, K = 0
J = 0, K = 1
Subjective questions:
- What is the difference between serial and parallel transfer? what type of register is used in each case?
- Why are shift registers considered to be basic memory devices?
- A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?
Advanced stage
Multiple choice questions:
- In a p stage shift register, what will be the final output delay if the clock period is t?
- Where will you give the pulse input in a ripple counter, designed with edge triggered JK flipflop?
- Calculate the maximum counting speed of a 4-bit binary counter designed with flipflops having 25 ns propagation delay
- The feedback loop in a counter reduces the number of inputs to reset the counter
- A mod-2 counter followed by a mod-5 counter is
p/t
t(p-1)
tp
t(2p-1)
J and K inputs of one flipflop
Clock input of one flipflop
Clock input of all the flipflops
None of these
100 MHz
4 MHz
50 MHz
10 MHz
True
False
Decade counter
mod-7 counter
mod-3 counter
Same as mod-5 counter followed by a mod-2 counter
Subjective questions:
- The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?
- A bidirectional 4-bit shift register is storing the nibble 1101. Its RIGHT/LEFT' input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, what the shift register will be storing?
- How many flip-flops are required to make a MOD-32 binary counter?
- A MOD-16 ripple counter is holding the count 1001. What will the count be after 31 clock pulses?
- What is the reason that synchronous counters eliminate the delay problems encountered with asynchronous counters?
Design of Registers and Counters :
Guideline to perform the experiment:Designing 4 bit shift register(serial in serial out)- Start the simulator as directed.This simulator supports 5-valued logic.
- To design a 4 bit shift register (right shift), we need 4 MSD flipflop, 1 free running clock, 1 Bit switch (which will act as input to the left most flipflop), 4 Bit display(to see the output of individual flipflops so that the shifting can be seen with the clock input), wires.
- The MSD flipflop component is in the sequential circuit drawer in the pallet. The pin configuration is shown whenever the mouse is hovered on any canned component of the palette or press the 'show pinconfig' button. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
- For MSD flipflop input is in pin-5, output(Q) is in pin-4, clock is in pin-8
- click on the MSD flipflop component in the pallet and then click on the position of the editor window where you want to add the component(no drag and drop, simple click will serve the purpose), likewise add 4 MSD flipflops, 1 free running clock, 1 Bit switche and 4 bit Displayes(from Display and Input drawer of the pallet,if it is not seen scroll down in the drawer)
- To connect any two components select the Connection menu of Palette, and then click on the Source terminal and click on the target terminal. connect all the components, connect the clock to the pin-8 of all the MSD flipflops, connect a bit switch to the pin-5(Q) of the left most MSD flipflop, connect 4 bit displayes to the pin-4 of 4 MSD flipflops, connect the Q output of the previous flipflop to the D(pin-5) input of the next flipflop.
- To see the circuit working, click on the Selection tool in the pallet then give input by double clicking on the bit switch, to the left most D flipflop at pi-5(let it be 1), start the clock now check the output and see how the 1 is shifting from left to right.
Components :
To build any register or counters, we need :
- Flip-Flops.
- Logic Gates.
- Wires to connect.
In case of counters the number of flip-flops depends on the number of different states in the counter.
Objective of designing registers:
- to understand the shifting of data
- to examine the behavior of different modes of data input and data output(serial-in serial-out, serial-in parallel-out, parallel-in serial out,parallel-in parallel-out)
- to make use of shift register in data transfer
- developing skills in the designing and testing of sequential logic circuits
- developing skills in analysing timing signals
Objective of designing counters:
- understanding the concept of counting upto certain limiting value and returning back to the start state from final state
- understanding the generation of timing sequences to control operations in a digital system
- developing skills in the design and testing of counters for given timing sequences
- developing skills in generating timing signals
Recommended learning activities for the experiment: Leaning activities are designed in two stages, a basic stage and an advanced stage. Accomplishment of each stage can be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module, secondly, on the module designed by the student, having gone through the theory, objective and procuder. By performing the experiment on the working module, students can only observe the input-output behavior. Where as, performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the input-output behavior. It is recommended to perform the experiments following the given guideline to check behavior and test plans along with their own circuit analysis. Then students are recommended to move on to the advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their knowledge base by further reading the references provided for the experiment.
- if value is UNKNOWN, wire color= maroon
- if value is TRUE, wire color= blue
- if value is FALSE, wire color= black
- if value is HI IMPEDENCE, wire color= green
- if value is INVALID, wire color= orange
Test plan:
- Give input and free running clock to the shift register as 10101 and check whether after 5 clock operation register output is set or not.
- Take a mod-6 counter. use free running clock and check whether after 6 clock operation register output is set or not.
Use Display units for checking output. Try to use minimum number of components to build. use free running clock input to the flip-flop. The pin configuration of the canned components are shown when mouse hovered over a component or by using 'show pinconfig'button.
Assignment Statements :
- Design 4-bit synchronous up and down counter.
- Design a 5-bit Shift Registers using the flip-flops and check the output.
- Design a 5-bit ring counter and a johnson counter.
- Design a mod-6 counter.
Design of Registers and Counters :
General guideline to use the simulator for performing the experiment:- Start the simulator as directed. For more detail please refer to the manual for using the simulator
- The simulator supports 5-valued logic
- To add the logic components to the editor or canvas (where you build the circuit) select any component and click on the position of the canvas where you want to add the component
- The pin configuration is shown when you select the component and press the 'show pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned component of palette
- To connect any two components select the connection tool of palette, and then click on the source terminal and then click on the the target terminal
- To move any component select the component using the selection tool and drag the component to the desired position
- To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a double click
- Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the output in digital format
- undo/redo, delete, zoom in/zoom out, and other functionalities have been given in the top toolbar for ease of circuit building
- Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can be set from the given 'set clock' button in the left toolbar
- Use 'plot graph' button to see input-output wave forms
- Users can save their circuits with .logic extension and reuse them
- After building the circuit press the simulate button in the top toolbar to get the output
- If the circuit contains a clock pulse input, then the 'start clock' button will start the simulation of the whole circuit. Then there is no need to again press the 'simulate' button
- If you are using linux platform then click on 'Linux(32 bit)' or if you are using then click on 'Windows(32 bit)'
- Start the simulator as directed.
- As the automated clock is under development and the simulator is under modification for sequencial circuits, we will use individual clock(bit switch which toggle its value with a double click) for each flipflop.
- To design the circuit we need 4 D flipflop, 5 Bit switch(4 will act as clock input to 4 flipflops and one will act as input to the left most flipflop), 4 Bit display(to see the output of individual flipflops so that the shifting can be seen with the clock input), wires.
- The D flipflop component is in the sequential circuit drawer in the pallet. The pin configuration is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
- For D flipflop input is in pin-5, output(Q) is in pin-4, clock is in pin-8
- click on the D flipflop component in the pallet and then click on the position of the editor window where you want to add the component(no drag and drop, simple click will serve the purpose), likewise add 4 D flipflops, 5 Bit switches and 4 bit Displayes(from Display and Input drawer of the pallet,if it is not seen scroll down in the drawer)
- To connect any two components select the Connection menu of Palette, and then click on the Source terminal and click on the target terminal. According to the circuit diagram(given in the theory) connect all the components, connect 4 bit switches to the pin-8 of 4 D flipflop, connect a bit switch to the pin-5 of the left most D flipflop, connect 4 bit displayes to the pin-4 of 4 D flipflops.
- To see the circuit working, click on the Selection tool in the pallet then give input by double clicking on the bit switch, to the left most D flipflop at pi-5(let it be 1) keeping all the clocks 0, now one by one change the clock value to 1 of the flipflops(from left to right) and see how the 1 is shifting from left to right.
Click here to download the older version of simulator
Click here to download the new version of simulator
OR
Launch the older version of Simulator
Launch the new version of Simulator
Once the simulator is downloaded, open the command prompt, then go to the directory where you have saved it using cd command and then give the following command to run the simulator:
java -jar coaSimulator.jar
- Start the simulator as directed.
- As the automated clock is under development and the simulator is under modification for sequencial circuits, we will use individual clock(bit switch which toggle its value with a double click) for each flipflop.
- To design the circuit we need 4 D flipflop, 5 Bit switch(4 will act as clock input to 4 flipflops and one will act as input to the left most flipflop), 4 Bit display(to see the output of individual flipflops so that the shifting can be seen with the clock input), wires.
- The D flipflop component is in the sequential circuit drawer in the pallet. The pin configuration is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
- For D flipflop input is in pin-5, output(Q) is in pin-4, clock is in pin-8
- click on the D flipflop component in the pallet and then click on the position of the editor window where you want to add the component(no drag and drop, simple click will serve the purpose), likewise add 4 D flipflops, 5 Bit switches and 4 bit Displayes(from Display and Input drawer of the pallet,if it is not seen scroll down in the drawer)
- To connect any two components select the Connection menu of Palette, and then click on the Source terminal and click on the target terminal. According to the circuit diagram connect all the components, connect 4 bit switches to the pin-8 of 4 D flipflop, connect a bit switch to the pin-5 of the left most D flipflop, connect 4 bit displayes to the pin-4 of 4 D flipflops. connect according to the circuit diagram shown in screenshot.
- To see the circuit working, click on the Selection tool in the pallet then give input by double clicking on the bit switch, to the left most D flipflop at pi-5(let it be 1) keeping all the clocks 0, now one by one change the clock value to 1 of the flipflops(from left to right) and see how the 1 is shifting from left to right.
Click here to download the older version of simulator
Click here to download the new version of simulator
OR
Launch the older version of Simulator
Launch the new version of Simulator
Once the simulator is downloaded, open the command prompt, then go to the directory where you have saved it using cd command and then give the following command to run the simulator:
java -jar Simulator.jar
Experiment-3 (Design of Registers and Counters) :
The web interface of the application is under development, so screenshots of the experiments are presented here.
This application is completely run under the platform independent editor frame.
As the clock input is under development, the complete simulation of registers and counters are not possible yet.
Design of Registers and Counters :
References :
Books:
- Digital Logic and Computer Design - M. Morris Mano. Pearson Education - Prentice Hall.
- Digital Principles Foundation of Circuit Design and Application - Arun Kumar Singh. New Age Publishers.
- The Art of Electronics - Paul Horowitz and Winfield Hill (1989). Cambridge University Press
- Modern Dictionary of Electronics - Rudolf F. Graf (1999). Newnes
Web Sites:
Virtual Lab is an initiative of Ministry of Human Resource and Development(MHRD) under National Mission of Education through ICT to provide an interactive environment over the internet for creating and conducting different laboratory experiments by sharing the costly equipments and the resources.
For more information about the Virtual Lab,please visit http://www.vlab.co.in/
Developers of Logic Design and Computer Organization Virtual Lab
- Dr. Chittaranjan Mandal Professor, Computer Science & Engineering
- Gargi Roy Senior Project Assistant
- Devleena Ghosh
Professor, Information Technology
IIT Kharagpur
Target Audience:
Under graduate students.
Courses Aligned With:
Computer organization and artitecture.
Pre-requisite Softwares:
- 32 bit java runtime environment and java 1.6 or above
- Recommended browser: mozilla firefox, google chrome
Objectives:
The Objective is to Expose the students to the various key aspects of Digital Logic and Computer Organisation by enabling them to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.
- Digital Logic and Computer Organisation are core courses in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline(Computer Science / Engg., Electronics, Electrical) etc.
- Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
- Even when such FPGA boards are available, making them available round the clock is difficult.
- Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
- Helps to standardize the set of Experiments to a large extent.
Contact Information:
Mailing Address and Contact Information:Department of Computer Science & Engineering, IIT Kharagpur
Office : +91-3222-2882255
Postal Address:
Indian Institute of Technology Kharagpur, Kharagpur - 721302, INDIA Telephone Number +91-3222-255221 | FAX : +91-3222-255303
Tutorial on UI for lab:
Introduction:
- The simulator contains a pallete on the right hand side. This pallete contains all the components and tools . Tools are used to act up on the components. Different tools:
- Selection tool- used for selecting components
- Marquee tool- used for selecting many components at a time by draggiung the mouse in the design area(editor).
- Connection tool- used for connecting components
- Components have been catagorized according to their functionality and put into different drawers in the pallete. The area under every drawer is scrallable, if you are unable to see all the components in a particular drawer just click on the area and scroll. Different drawers:
- Circuits- contains 8 and 16 terminal circuits and flow container which can hold other circuit components.
- Logic gates- contains all kinds of basic logic gates.
- Display and inputs- contains all kinds of component needed to give input to the circuit and displaying outputs of the circuit.
- Adders- contains different types of adder circuits.
- Sequential ckt- contains basic flipflops for designing sequential circuits.
- Other Components- contains different kinds of components like decoders, multiplexers, arithmetic logic units(ALU), memory elements(RAM cell) required to design combinational circuits.
- To add the components to the editor select any component(first click on the selection tool then click on the desired compoent) then finally click on the position of the editor window where you want to add the component.
- The pin configuration of a component is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
- To connect any two components select the Connection tool in the palette, and then click on the Source terminal and click on the target terminal(no drag and drop, simple click will serve the purpose). After the connection is over click the selection tool in the pallete.
- To move any components select the Selection Mode and drag the component after selecting it.
- If needed select any component in the editor while designing your circuit and use Undo, Redo, Delete, Zoom in, Zoom out buttons to get corresponding functionalities. Open and Save options are under development.
- As the automated clock is under development and the simulator is under modification for sequencial circuits, for the time being please use individual clock(Bit switch which toggle its value with a double click) for each flipflop.
- The simulator is currently under modification for sequential circuits, now it is working properly for combinational circuits but may not give proper output for sequential circuits.
Description of Components:
General components:- Digital display: it can be used to give input and as well as to see the output in the decimal format, its right most terminal is the LSB(least significant bit) and the left most terminal is the MSB(most significant bit), in the editor after selecting a particular digital display you can use 'Increment LED' and 'Decrement LED' buttons in the top left corner of the simulator to increment and decrement its value respectively.
- Bit display: it displays a single bit value.
- V+: it gives 1 as input.
- Ground: it gives 0 as input.
- Bit switch: it gives 1/0 input, it toggels its value with a double click.
Specific components:
Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise. Pin configurations of all the components-
- Half adder: i/p: 5,8 o/p: sum=4, carry=1
- Full adder: i/p: 5,6,8 o/p: sum=4, carry=1
- RCA 4 bit: (4 bit ripple carry adder) i/p: A0=13,A1=14,A2=15,A3=16; B0=17,B1=18,B2=19,B3=20; C0=21 o/p: S0=12,S1=11,S2=10,S3=9,Cout=8
- Wallace tree adder: (adds 3 4-bit numbers) i/p: A0=13,A1=14,A2=15,A3=16; B0=17,B1=18,B2=19,B3=20; C0=21,C1=22,C2=23,C3=24 o/p: S0=12,S1=11,S2=10,S3=9,Cout=8
- RS flipflop: i/p: R=5, S=8, Clk=7 o/p: Q=4, Q'=1
- D flipflop: i/p: D=5, Clk=8 o/p: Q=4, Q'=1
- T flipflop: i/p: T=8, Clk=7 o/p: Q=4, Q'=1
- JK flipflop: i/p: J=5, K=8, Clk=7 o/p: Q=4, Q'=1
- 2:4 Decoder: i/p: A0=5,A1=7 o/p: D0=4,D1=3,D2=2,d3=1
- 2:4 Decoder with enable: i/p: A=6,B=5, Enable=8 o/p: D0=4,D1=3,D2=2,d3=1
- 4:1 Mux: i/p: I0=9,I1=10,I2=11,I3=12,S0=13,S1=14 o/p: F=8
- Combinational Multiplier: i/p: multiplicand: A0=13,A1=14,A2=15,A3=16 Multiplier: B0=9,B1=10,B2=11,B3=12 o/p: S0=8,S1=7,S2=6,S3=5,S4=4,S5=3,S6=2,S7=1
- ALU 1 bit: i/p: A0=9, B0=10, C0=21 S0=12,S1=13 o/p: F=8, Cout=7
- 4 bit ALU: i/p: A0=13,A1=14,A2=15,A3=16; B0=17,B1=18,B2=19,B3=20; C0=21;S0=22,S1=23 o/p: F0=12,F1=11,F2=10,F3=9,Cout=8
- 16 bit ALU: i/p: A1=13,A2=15; B1=14,B2=16; Cin=9,S0=12,S1=11,S2=10 o/p: Cout=6,F2=7,F1=8
- RAM Cell: i/p=5, select=8, R/W'=6, o/p=4, R/W'=1 for read operation, R/W'=0 for write operation
- IC Memory: R/W'=16 Memory Enable=15, Address i/p=14,13 Data i/p=12,11,10 Data o/p=6,7,8 R/W'=1 for read operation, R/W'=0 for write operation
- Direct Mapped Cache:
- pin-32= S(selects whether user wants to perform cache write or cache mapping)
- pin-31= R/W'A(selects whether user wants to input the address or cache mapping)
- pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (thise 4 pins are used to give address input). A3 is the most significant bit and A0 is the least significant bit. A3 and A2 will be compared with the tag. A1 and A0 will select the corrsponding set.
- pin-26= R/W'D(selects whether user wants to input in the set of cache or cache mapping)
- pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the least significant bit). thiese two bits are used for cache writhe purpose, it selects the particular set of which user wants to give inputs to the valid bit, tag bits and data bits.
- pin-23= Den(this is an enable input which has to set for any write purpose in the cache).
- pin-21= valid bit
- pin-20= T1, pin-19=T0 (T1 is the most significant bit and T0 is the least significant bit). These are tag bits.
- pin-18= D1, pin-17=D0 (D1 is the most significant bit and D0 is the least significant bit). These are data bits.
- pin-14= Hit/Miss bit(if it gives 1 then hit otherwise miss)
- pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the least significant bit). These are output data bits and will be given only when there is a hit.
- Essential pin configurations for writing in cache: S=1, R/W'A=0, R/W'D=0, Den= 1
- Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1, Den= 0
Testing process:
- To test your circuit give some input(through Digital display or Bit switch or V+ or Ground), if you use the Digital display or Bit switch you can then give different input to you circuit through incrementing/decrementing the Digital display or double clicking the Bit switch, the other two gives constant inputs.
- to see the output, connect Digital display or Bit display to the output terminals of your circuit.
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Frequently Asked Questions:
What is virtual lab?
The Virtual Laboratory is an interactive environment for creating and conducting simulated experiments: a playground for experimentation. It consists of domain dependent simulation programs, experimental units called objects that encompass data files, tools that operate on these objects.
What are the advantages of virtual lab?
Virtual Logic Design and Computer Organisation lab enables students to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.
- Digital Logic and Computer Organisation are core courses in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline ( Computer Science / Engg., Electronics, Electrical ] etc.
- Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
- Even when such FPGA boards are available, making them available round the clock is difficult.
- Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
- Helps to standardize the set of Experiments to a large extent.
What is eclipse platform?
Eclipse is a Java-based, extensible open source development platform. By itself, it is simply a framework and a set of services for building a development environment from plug-in components. Eclipse comes with a standard set of plug-ins, including the Java Development Tools (JDT).
Which framework is used to develop the application?
We have used the eclipse gef framework. The Graphical Editing Framework (GEF) allows developers to take an existing application model and quickly create a rich graphical editor.
What is platform independent application?
Applications that run under particular operating systems and/or particular hardwares are called platform dependent application whereas platform independent applications can run in any operating environment.
What are the experiments which can be performed by the Virtual Logic Design and Computer Organization lab?
The experiments that will be supported by this lab are given below:
- Design of a ripple carry adder
- Design of a carry-look-ahead adder
- Design of registers and counters
- Design of a wallace tree adder
- Design of combinational multipliers
- Design of a Booth’s multiplier
- Design of an ALU
- Design of memory units
- Design of direct mapped cache
- Design of associative cache
- Design of combinational dividers
- CPU design