Virtual Lab - IIT Kharagpur

Design of Direct Mapped Cache :

Cache memory is a small (in size) and very fast (zero wait state) memory which sits between the CPU and main memory. The notion of cache memory actually rely on the correlation properties observed in sequences of address references generated by CPU while executing a programm(principle of locality).When a memory request is generated, the request is first presented to the cache memory, and if the cache cannot respond, the request is then presented to main memory.

• Hit: a cache access finds data resident in the cache memory
• Miss: a cache access does not find data resident, so it forces to access the main memory.

Cache treats main memory as a set of blocks.As the cache size is much smaller than main memory so the number of cache lines are very less than the number of main memory blocks. So a procedure is needed for mapping main memory blocks into cache lines.cache mapping scheme affects cost and performance. There are three methods in block placement-

• Direct Mapped Cache
• Fully Associative Mapped Cache
• Set Associative Mapped Cache

Direct Mapped Cache

A given memory block can be mapped into one and only cache line.

Block identification: let the main memory contains n blocks(which require log₂(n)) and cache contains m blocks, so n/m different blocks of memory can be mapped (at different times) to a cache block. Each cache block has a tag saying which block of memory is currently present in it, each cache block also contain a valid bit to ensure whether a memory block is in the cache block currently.

• Number of bits in the tag: log₂(n/m)
• Number of sets in the Cache: m
• Number of bits to identify the correct set: log₂(m)

The memory address is divided into 3 parts- tag(most MSB), index, block offset(most LSB) in order to do the cache mapping.

Select set using index, block from set using tag.

Select location from block using block offset.

tag + index = block address

Diagram of a direct mapped cache (here main memory address is of 32 bits and it gives a data chunk of 32 bits at a time):

If a miss occur CPU bring the block from the main memory to the cache, if there is no free block in the corresponding set it replaces a block and put the new one. CPU uses different replacement policies to decide which block is to replace. The disadvantage of the direct mapped cache is that it is easy to build, but suffer the most from thrashing due to the 'conflict misses' giving more miss penalty.

Design issues:

Bellow is a simple cache which holds 1024 words or 4KB, memory address is 32 bits. The tag from the cache is compared against the most significant bits of the address to determine whether the entry in the cache corresponds to the requested address as the cache has 2¹⁰ or 1024 words and a block size of one word, 10 bits are used to index the cache, leaving 32-10-2=20 bits to be compared against the tag. If the tag and the most significant 20 bits of the address are equal and the valid bit is on then the request hits in the cache otherwise miss occurs. No replacement policy has been implemented in the circuit.

The comparator Circuit through which tag is compared with specified bits of address:

Design of Direct Mapped Cache :

Basic stage

Multiple choice questions:

• Special high-speed memory reserved for the temporary storage of the data or instructions likely to be needed next by the processor is cache memory

True

False

---

• Cache memory improves performance due to the locality of reference behavior of a program

True

False

---

• Property of locality of reference may fail, if a program has

Many Operators

Many conditional jumps

Many operands

Many unconditional jumps

---

• Data can be placed at any position in direct mapped cache

True

False

• Direct mapped cache reduces the hardware cost with introducing some restrictions on which position a data can be stored

True

False

• Unified cache has lower hit rate

True

False

---

Subjective questions:

• What is the difference between direct mapping, associative mapping and set-associative mapping?
• How does the principle of locality relate to the design of multiple memory levels?
• What is the difference between temporal locality and spatial locality?
• How many different blocks of memory can be mapped if the main memory contains n blocks and cache contains m blocks?
• What is the number of bits in the tag field if the main memory contains n blocks and cache contains m blocks?

Advanced stage

Multiple choice questions:

• In k-way associative mapping, if k=1, then it becomes direct mapping

True

False

---

• If memory has an access time of 100ns, access time of the cache memory is 40ns with 80% hit ratio, then what is the effective access time of the CPU?

60ns

50ns

90ns

55ns

---

• Tag bits in direct mapping (assume, p is number of main memory blocks and q is number of cache blocks)

log(pq)

logp

log(p/q)

None of these

---

• How many lines are there in a direct mapped cache having 23-bit tag and 1-word blocks?

512 bytes

256 bytes

1024 bytes

None of these

---

• Consider a memory system with cache and main memory. The cache is 5 times faster than the main memory, its hit ratio is 80%. If average access time is increased by 20% from 50ns, then will there be any change in hit ratio, if yes, how much?

No change

Yes, Increase by 20%

Yes, Decreases by 10%

None of these

---

Subjective questions:

• A direct mapped cache consists of 16 blocks. main memory contains 16K blocks of 8 bytes each. What is the main memory address format i.e the size of each field?
• For a direct mapped cache design with 32-bit address, the following bits of address are used to access the cache. (1 word = 4 bytes): tag=31-14, index=13-6, offset=5-0. answer the following-
  1. What is the cache block size (in words)?
  2. What is the size of the cache?
• What are the advantages of using direct mapped cache?

Design of Direct Mapped Cache :

Procedure to perform the experiment for Direct mapped cache on the existing component 'Direct Mapped Cache' component in the 'other components' drawer in the simulator.This simulator supports 5-valued logic.

Bellow is a schematic diagram of the 'Direct Mapped Cache' component in the 'other components' drawer in the simulator:

1. Click on the 'Direct Mapped Cache' component(in the 'other components' drawer in the pallet) and then click on the position of the editor window where you want to add the component(no drag and drop, simple click will serve the purpose), likewise add 15 Bit switches and 3 Bit Displays(from Display and Input drawer of the pallet,if it is not seen scroll down in the drawer)
2. 'Direct Mapped Cache' component in the 'other components' drawer in the simulator supports both writing in the cache and the cache mapping. No replacement policy has been implemented. Initially the cache is empty, user has to give inputs. the component contains 4 sets, each set has 5 bits, the left most bit is the valid bit, next 2 bits are tags, next bits are data bits, also it contains a one dimensional array of memory with 4 bit to store the memory address, user has to give this address input also.the cache reads all the data bits at a time so block offset is not required.
3. The pin configuration of the component can be seen whenever the mouse is hovered on any canned component of the palette or press the 'show pinconfig' button. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
4. For a 'Direct Mapped Cache' component pin configuration is:
• pin-32= S (selects whether user wants to perform cache write or cache mapping)
• pin-31= R/W'A (selects whether user wants to input the address or cache mapping)
• pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (these 4 pins are used to give address input). A3 is the most significant bit and A0 is the least significant bit. A3 and A2 will be compared with the tag. A1 and A0 will select the corrsponding set.
• pin-26= R/W'D(selects whether user wants to input in the set of cache or cache mapping)
• pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the least significant bit). thiese two bits are used for cache write purpose, it selects the particular set of which user wants to give inputs to the valid bit, tag bits and data bits.
• pin-23= Den (this is an enable input which has to set for any write purpose in the cache).
• pin-21= valid bit
• pin-20= T1, pin-19=T0 (T1 is the most significant bit and T0 is the least significant bit). These are tag bits.
• pin-18= D1, pin-17=D0 (D1 is the most significant bit and D0 is the least significant bit). These are data bits.
• pin-14= Hit/Miss bit (if it gives 1 then hit otherwise miss)
• pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the least significant bit). These are output data bits and will be given only when there is a hit.
5. Essential pin configurations for writing in the cache: S=1, R/W'A=0, R/W'D=0, Den= 1
6. Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1, Den= 0
7. To connect any two components select the Connection menu of Palette, and then click on the Source terminal and click on the target terminal. According to the circuit diagram connect all the components. After the connection is over click the selection tool in the pallete.
8. See the output, Bit switches are used to give input so that you can toggle its value with a double click and see the outputs with different inputs.

Screenshot of the experiment

Components :

To build a Direct Mapped Cache with 4 bit memory address and 2 bit data address without any replacement policy, we need :

1. Decoder with enable and decoder without enable
2. Multiplexer with enable and multiplexer without enable
3. Single bit memory elements
4. XOR gates, NOR gates, AND gates
5. Bit switches to give inputs
6. Display units to check the outputs.
7. Wires to connect.

Objective of direct mapped cache design:

1. Understanding behaviour of direct mapped cache from working module
2. Designing a direct mapped cache for given parameters

Examining behaviour of given direct mapped cache

• number of tag bits: 2
• modulus value arising from given tag bits: 2²=4
• number of bits in set component of address: 2
• number of bits in block component: 0

Loading data in the cache (refer to procedure tab for pin numbers)

• global initialisation: (S=1, R/W'A=0, R/W'D=0, Den=1)
• in cache line 0, load as follows:
  • data= "11" (D1=1, D0=1)
  • tag= "10" (T0=0, T1=1)
  • valid bit= "1" (valid=1)
• in cache line 1, load as follows:
  • valid bit= "0" (valid=1)

Examining hit behaviour

• load data in address latch as:
  • set: "00" (A0=0, A1=0),
  • tag= "10" (A3=1, A2=0)
• initiate cache mapping:
  • S=0, R/W'A=1, R/W'D=1, Den= 0
• check output:
  • F0=1, F1=1, hit/miss=1

Examining miss behaviour due to mismatch of tag:

• load data in address latch as:
  • set: "00" (A0=0, A1=0),
  • tag= "11" (A3=1, A2=1)
• initiate cache mapping:
  • S=0, R/W'A=1, R/W'D=1, Den= 0
• check output:
  • F0=0, F1=0, hit/miss=0

Examining miss behaviour due to valid bit not set:

• load data in address latch as:
  • set: "01" (A0=1, A1=0),
  • tag= "11" (A3=1, A2=1)
• initiate cache mapping:
  • S=0, R/W'A=1, R/W'D=1, Den= 0
• check output:
  • F0=0, F1=0, hit/miss=0

Recommended learning activities for the experiment: Leaning activities are designed in two stages, a basic stage and an advanced stage. Accomplishment of each stage can be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module, secondly, on the module designed by the student, having gone through the theory, objective and procuder. By performing the experiment on the working module, students can only observe the input-output behavior. Where as, performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the input-output behavior. It is recommended to perform the experiments following the given guideline to check behavior and test plans along with their own circuit analysis. Then students are recommended to move on to the advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their knowledge base by further reading the references provided for the experiment.

color configuration of wire for 5 valued logic supported by the simulator:

• if value is UNKNOWN, wire color= maroon
• if value is TRUE, wire color= blue
• if value is FALSE, wire color= black
• if value is HI IMPEDENCE, wire color= green
• if value is INVALID, wire color= orange

Test Plan :

1. give some valid input initially in the cache then give such address so that hit occurs then alter the address content or the tag or valid bit to get a miss.
2. Use Display units for checking output. Try to use minimum number of components to build. The pin configuration of the canned components are shown when mouse hovered over a component.

Assignment Statements :

You are required to build the following direct mapped cache:

1. cache with one word, 4 bit memory address, 2 bit data without repacement policy.
2. cache with 8 bit memory address, 8 bit data without repacement policy.
3. cache with each set containing multiple words without repacement policy.

Design of Direct Mapped Cache :

General guideline to use the simulator for performing the experiment:

• Start the simulator as directed. For more detail please refer to the manual for using the simulator
• The simulator supports 5-valued logic
• To add the logic components to the editor or canvas (where you build the circuit) select any component and click on the position of the canvas where you want to add the component
• The pin configuration is shown when you select the component and press the 'show pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned component of palette
• To connect any two components select the connection tool of palette, and then click on the source terminal and then click on the the target terminal
• To move any component select the component using the selection tool and drag the component to the desired position
• To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a double click
• Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the output in digital format
• undo/redo, delete, zoom in/zoom out, and other functionalities have been given in the top toolbar for ease of circuit building
• Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can be set from the given 'set clock' button in the left toolbar
• Use 'plot graph' button to see input-output wave forms
• Users can save their circuits with .logic extension and reuse them
• After building the circuit press the simulate button in the top toolbar to get the output
• If the circuit contains a clock pulse input, then the 'start clock' button will start the simulation of the whole circuit. Then there is no need to again press the 'simulate' button
• If you are using linux platform then click on 'Linux(32 bit)' or if you are using then click on 'Windows(32 bit)'

Linux(32 bit)

Windows(32 bit)

Screenshot of direct mapped cache design:

Back

Guideline to perform the experiment for Direct mapped cache on the existing component 'Direct Mapped Cache' component in the 'other components' drawer in the simulator.

Bellow is a schematic diagram of the 'Direct Mapped Cache' component in the 'other components' drawer in the simulator:

1. Click on the 'Direct Mapped Cache' component (in the 'other components' drawer in the pallet) and then click on the position of the editor window where you want to add the component (no drag and drop, simple click will serve the purpose), likewise add 15 Bit switches and 3 Bit Displays(from Display and Input drawer of the pallet,if it is not seen scroll down in the drawer)
2. 'Direct Mapped Cache' component in the 'other components' drawer in the simulator supports both writing in the cache and the cache mapping. No replacement policy has been implemented. Initially the cache is empty, user has to give inputs. the component contains 4 sets, each set has 5 bits, the left most bit is the valid bit, next 2 bits are tags, next bits are data bits, also it contains a one dimensional array of memory with 4 bit to store the memory address, user has to give this address input also.the cache reads all the data bits at a time so block offset is does not require.
3. The pin configuration of the component can be seen whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner (indicated with the circle) and increases anticlockwise.
4. For a 'Direct Mapped Cache' component pin configuration is:
• pin-32= S (selects whether user wants to perform cache write or cache mapping)
• pin-31= R/W'A(selects whether user wants to input the address or cache mapping)
• pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (these 4 pins are used to give address input). A3 is the most significant bit and A0 is the least significant bit. A3 and A2 will be compared with the tag. A1 and A0 will select the corrsponding set.
• pin-26= R/W'D (selects whether user wants to input in the set of cache or cache mapping)
• pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the least significant bit). thiese two bits are used for cache writhe purpose, it selects the particular set of which user wants to give inputs to the valid bit, tag bits and data bits.
• pin-23= Den (this is an enable input which has to set for any write purpose in the cache).
• pin-21= valid bit
• pin-20= T1, pin-19=T0 (T1 is the most significant bit and T0 is the least significant bit). These are tag bits.
• pin-18= D1, pin-17=D0 (D1 is the most significant bit and D0 is the least significant bit). These are data bits.
• pin-14= Hit/Miss bit (if it gives 1 then hit otherwise miss)
• pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the least significant bit). These are output data bits and will be given only when there is a hit.
5. Essential pin configurations for writing in the cache: S=1, R/W'A=0, R/W'D=0, Den= 1
6. Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1, Den= 0
7. To connect any two components select the Connection menu of Palette, and then click on the Source terminal and click on the target terminal. According to the circuit diagram connect all the components. After the connection is over click the selection tool in the pallete.
8. See the output, Bit switches are used to give input so that you can toggle its value with a double click and see the outputs with different inputs.

Screenshot of the experiment

Click here to download the older version of simulator

Click here to download the new version of simulator

OR

Launch the older version of Simulator

Launch the new version of Simulator

Once the simulator is downloaded, open the command prompt, then go to the directory where you have saved it using cd command and then give the following command to run the simulator:
java -jar coaSimulator.jar

Objective:

Direct mapping assigned each memory block to a specific line in the cache not in any arbitrary line.

Guideline to perform the experiment for Direct mapped cache on the existing component 'Direct Mapped Cache' component in the 'other components' drawer in the simulator.

Bellow is a schematic diagram of the 'Direct Mapped Cache' component in the 'other components' drawer in the simulator:

1. Click on the 'Direct Mapped Cache' component (in the 'other components' drawer in the pallet) and then click on the position of the editor window where you want to add the component (no drag and drop, simple click will serve the purpose), likewise add 15 Bit switches and 3 Bit Displays(from Display and Input drawer of the pallet,if it is not seen scroll down in the drawer)
2. 'Direct Mapped Cache' component in the 'other components' drawer in the simulator supports both writing in the cache and the cache mapping. No replacement policy has been implemented. Initially the cache is empty, user has to give inputs. the component contains 4 sets, each set has 5 bits, the left most bit is the valid bit, next 2 bits are tags, next bits are data bits, also it contains a one dimensional array of memory with 4 bit to store the memory address, user has to give this address input also.
3. The pin configuration of the component can be seen whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner (indicated with the circle) and increases anticlockwise.
4. For a 'Direct Mapped Cache' component pin configuration is:
• pin-32= S (selects whether user wants to perform cache write or cache mapping)
• pin-31= R/W'A (selects whether user wants to input the address or cache mapping)
• pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (these 4 pins are used to give address input). A3 is the most significant bit and A0 is the least significant bit. A3 and A2 will be compared with the tag. A1 and A0 will select the corrsponding set.
• pin-26= R/W'D (selects whether user wants to input in the set of cache or cache mapping)
• pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the least significant bit). thiese two bits are used for cache writhe purpose, it selects the particular set of which user wants to give inputs to the valid bit, tag bits and data bits.
• pin-23= Den (this is an enable input which has to set for any write purpose in the cache).
• pin-21= valid bit
• pin-20= T1, pin-19=T0 (T1 is the most significant bit and T0 is the least significant bit). These are tag bits.
• pin-18= D1, pin-17=D0 (D1 is the most significant bit and D0 is the least significant bit). These are data bits.
• pin-14= Hit/Miss bit (if it gives 1 then hit otherwise miss)
• pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the least significant bit). These are output data bits and will be given only when there is a hit.
5. Essential pin configurations for writing in the cache: S=1, R/W'A=0, R/W'D=0, Den= 1
6. Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1, Den= 0
7. To connect any two components select the Connection menu of Palette, and then click on the Source terminal and click on the target terminal. According to the circuit diagram connect all the components. After the connection is over click the selection tool in the pallete.
8. See the output, Bit switches are used to give input so that you can toggle its value with a double click and see the outputs with different inputs.

Screenshot of the experiment

Click here to download the older version of simulator

Click here to download the new version of simulator

OR

Launch the older version of Simulator

Launch the new version of Simulator

Once the simulator is downloaded, open the command prompt, then go to the directory where you have saved it using cd command and then give the following command to run the simulator:
java -jar Simulator.jar

Design of Direct Mapped Cache :

References :

Books:

1. Computer Organization and Architecture - William Stallings
2. Computer System Architecture - M. Morris Mano
3. Computer Architecture and Organization - John P. Hayes
4. Digital Logic and Computer Design - M. Morris Mano. Pearson Education - Prentice Hall.
5. Digital Principles Foundation of Circuit Design and Application - Arun Kumar Singh. New Age Publishers.
6. The Art of Electronics - Paul Horowitz and Winfield Hill (1989). Cambridge University Press
7. Modern Dictionary of Electronics - Rudolf F. Graf (1999). Newnes

Web Sites:

• NPTEL (e-learning courses from IITs and IISC)

Virtual Lab is an initiative of Ministry of Human Resource and Development(MHRD) under National Mission of Education through ICT to provide an interactive environment over the internet for creating and conducting different laboratory experiments by sharing the costly equipments and the resources.

For more information about the Virtual Lab,please visit http://www.vlab.co.in/

Developers of Logic Design and Computer Organization Virtual Lab

• Dr. Chittaranjan Mandal
Professor, Computer Science & Engineering
Professor, Information Technology
IIT Kharagpur
• Gargi Roy
Senior Project Assistant
• Devleena Ghosh

Target Audience:

Under graduate students.

Courses Aligned With:

Computer organization and artitecture.

Pre-requisite Softwares:

• 32 bit java runtime environment and java 1.6 or above
• Recommended browser: mozilla firefox, google chrome

Objectives:

The Objective is to Expose the students to the various key aspects of Logic Design and Computer Organisation by enabling them to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.

1. Digital Logic and Computer Organisation happens to be a Core Course in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline(Computer Science / Engg., Electronics, Electrical) etc.
2. Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
3. Even when such FPGA boards are available, making them available round the clock is difficult.
4. Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
5. Helps to standardize the set of Experiments to a large extent.

Feedback:

To give your feedback please visit the following link-

Sponsered by MHRD (NME-ICT) .

Tutorial on UI for lab:

Introduction:

1. The simulator contains a pallete on the right hand side. This pallete contains all the components and tools . Tools are used to act up on the components. Different tools:
   • Selection tool- used for selecting components
   • Marquee tool- used for selecting many components at a time by draggiung the mouse in the design area(editor).
   • Connection tool- used for connecting components
2. Components have been catagorized according to their functionality and put into different drawers in the pallete. The area under every drawer is scrallable, if you are unable to see all the components in a particular drawer just click on the area and scroll. Different drawers:
• Circuits- contains 8 and 16 terminal circuits and flow container which can hold other circuit components.
• Logic gates- contains all kinds of basic logic gates.
• Display and inputs- contains all kinds of component needed to give input to the circuit and displaying outputs of the circuit.
• Adders- contains different types of adder circuits.
• Sequential ckt- contains basic flipflops for designing sequential circuits.
• Other Components- contains different kinds of components like decoders, multiplexers, arithmetic logic units(ALU), memory elements(RAM cell) required to design combinational circuits.
3. To add the components to the editor select any component(first click on the selection tool then click on the desired compoent) then finally click on the position of the editor window where you want to add the component.
4. The pin configuration of a component is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
5. To connect any two components select the Connection tool in the palette, and then click on the Source terminal and click on the target terminal(no drag and drop, simple click will serve the purpose). After the connection is over click the selection tool in the pallete.
6. To move any components select the Selection Mode and drag the component after selecting it.
7. If needed select any component in the editor while designing your circuit and use Undo, Redo, Delete, Zoom in, Zoom out buttons to get corresponding functionalities. Open and Save options are under development.
8. As the automated clock is under development and the simulator is under modification for sequencial circuits, for the time being please use individual clock(Bit switch which toggle its value with a double click) for each flipflop.
9. The simulator is currently under modification for sequential circuits, now it is working properly for combinational circuits but may not give proper output for sequential circuits.

Description of Components:

General components:

1. Digital display: it can be used to give input and as well as to see the output in the decimal format, its right most terminal is the LSB(least significant bit) and the left most terminal is the MSB(most significant bit), in the editor after selecting a particular digital display you can use 'Increment LED' and 'Decrement LED' buttons in the top left corner of the simulator to increment and decrement its value respectively.
2. Bit display: it displays a single bit value.
3. V+: it gives 1 as input.
4. Ground: it gives 0 as input.
5. Bit switch: it gives 1/0 input, it toggels its value with a double click.

Specific components:

Testing process:

1. To test your circuit give some input(through Digital display or Bit switch or V+ or Ground), if you use the Digital display or Bit switch you can then give different input to you circuit through incrementing/decrementing the Digital display or double clicking the Bit switch, the other two gives constant inputs.
2. to see the output, connect Digital display or Bit display to the output terminals of your circuit.

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Frequently Asked Questions:

What is virtual lab?

The Virtual Laboratory is an interactive environment for creating and conducting simulated experiments: a playground for experimentation. It consists of domain dependent simulation programs, experimental units called objects that encompass data files, tools that operate on these objects.

What are the advantages of virtual lab?

Virtual Logic Design and Computer Organisation lab enables students to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.

1. Digital Logic and Computer Organisation happens to be a Core Course in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline ( Computer Science / Engg., Electronics, Electrical ] etc.
2. Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
3. Even when such FPGA boards are available, making them available round the clock is difficult.
4. Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
5. Helps to standardize the set of Experiments to a large extent.

What is eclipse platform?

Eclipse is a Java-based, extensible open source development platform. By itself, it is simply a framework and a set of services for building a development environment from plug-in components. Eclipse comes with a standard set of plug-ins, including the Java Development Tools (JDT).

Which framework is used to develop the application?

We have used the eclipse gef framework. The Graphical Editing Framework (GEF) allows developers to take an existing application model and quickly create a rich graphical editor.

What is platform independent application?

Applications that run under particular operating systems and/or particular hardwares are called platform dependent application whereas platform independent applications can run in any operating environment.

What are the experiments which can be performed by the Virtual Logic Design and Computer Organization lab?

The experiments that will be supported by this lab are given below:

1. Design of a ripple carry adder
2. Design of a carry-look-ahead adder
3. Design of registers and counters
4. Design of a wallace tree adder
5. Design of combinational multipliers
6. Design of a Booth’s multiplier
7. Design of an ALU
8. Design of memory units
9. Design of direct mapped cache
10. Design of associative cache
11. Design of combinational dividers
12. CPU design