Virtual Lab - IIT Kharagpur

Synthesis of flip-flops:

Till now the experiments are based only on the combinational circuits where output at any instance depends only on the current input. Most of components of digital logic consists combinational circuits but they likely to have memory elements too. Those type of circuits are known to be sequential circuits. In a sequential circuit the present output is not only determined by the present input but also depends on the past output. flip-flops are the simplest kind of sequential circuits. A flip-flop can maintain a binary state identity which means it can act as 1-bit memory cell. There are different kind of flip-flops depending on the number of inputs or the way the inputs affect the states.

Basic flip-flop : A basic flip-flop circuit can be constructed using two cross-coupled NAND/NOR gates shown below . Each flip-flop has two outputs, Q and Q', and two inputs, set and reset. When the set input goes to 1 the Q output goes to 1 and the Q' goes to 1 when reset goes to 1. But when both set, reset are 1, both Q, Q' outputs go to 0 for basic flip-flop circuit with NOR gates. In basic flip-flop circuit with NAND gates, when both input go to 0, both outputs go to 0 violating the fact that the outputs of the flip-flop have to be complement of each other.

There are various different kind of flip-flops. Some of the common flip-flops are: R-S flip-flop, D flip-flop, J-K flip-flop, T flip-flop etc.

1. Clocked RS flip-flop : The basic flip-flop is modified by adding some gates to the inputs so that the flip-flop changes state only when the clock pulse is 1. The truth table for this type of flip-flop is shown below. If R is high then reset state occurs and when S=1 then set state. However, if both the inputs are 1 then it violates normal operation of flip-flop.

   

2. JK flip-flop JK flip-flop is a refinement of RS flip-flop where the indeterminate state of RS type is defined. Input J and K are respectively the set and reset inputs of the flip-flop. When both the inputs are high then the output of the flip-flop switches to its complemented state.A clocked JK flip-flop is shown below. In level triggred JK flip-flops, at J=1 and K=1, a timimg problem, known as race around condition arises which can be explained by the following diagram. Let the width of a clock pulse is t_p and the current output Q is 1. when the clock is applied, after the propagation delay, say dt, the output will toggle and now the output Q will be 0. If dt is less than t_p, then after dt the output Q will again toggle and become 1. Thus the output will oscillate between 0 and 1 within the t_p interval, so at the end of the clock pulse t_p, the output will be ambiguous.

   

   Master slave JK flip-flop overcome this race around condition. The following figure depicts the circuit diagram.

   

   However, the master slave circuit, though handles race around condition, it may work improperly initially, if it has inconsistent initialization. Ideally, initially the master and the slave should have the same value, but if it does not, then it leads to inconsistent initialization, for which the circuit behaves improperly. Bellow is a case showing the improper output for an inconsistent initialization. Here, at clock=1, the master is supposed to change its state acordingly, but.......

   

   

   

   The problem occured due to the inconsistent initialization in the master slave JK flip-flop can be avoided by asynchronously presetting or clearing the flip-flop. The circuit diagram is shown bellow.

   

3. D flip-flop The D flip-flop is used to transfer data to the flip-flop. It is basically the JK flip-flop where the the K input is inverted. The circuit diagram of the D flip-flop is shown below,
4. Tflip-flop The T or "toggle" flip-flop changes its output on each clock edge. The truth table as follows:

Synthesis of flip-flops:

Basic stage

Multiple choice questions:

Synthesis of flip-flops:

1. Start the simulator as directed.This simulator supports 5-valued logic.
2. The experiment is needed to be performed on the given structural working modules of all kinds of flip-flops.
3. The flip-flop components are in the sequential circuit drawer in the pallet. The pin configuration is shown whenever the mouse is hovered on any canned component of the palette or press the 'show pinconfig' button. Pin numbering starts from 1 and from the bottom left corner (indicated with the circle) and increases anticlockwise.
4. Click on the flip-flop component in the pallet and then click on the position of the editor window where you want to add the component (no drag and drop, simple click will serve the purpose), likewise add free running clock, bit switches and bit displays (from Display and Input drawer of the pallet, if it is not seen scroll down in the drawer)
5. To connect any two components select the Connection menu of palette, and then click on the source terminal and click on the target terminal. connect all the components, connect the clock to the clock port of the flip-flop, connect bit switches to the proper input ports of the flip-flop, connect bit displayes to the proper output ports of the flip-flop.
6. To see the circuit working, click on the selection tool in the pallet then give input by double clicking on the bit switch, turn on the case analysis feature in the simulator if the pin configuration of that flip-flop mentions the case analysis as required, then start the clock now check behavior of the flip-flop according the guideline given in the objective.

Components :

To build any gate level flip-flop, we need :

1. Logic Gates.
2. Wires to connect.

Objective of synthesis of flip-flops:

1. to understand the basic concepts of flip-flops as elementary units of sequential circuits
2. to understand what is race around condition and why does it occur in JK flip-flop
3. to know how the race around condition which occures in JK flip-flop is avoided
4. to understand what kind of problems may occur in master slave JK flip-flop
5. to know the need for master slave JK flip-flop with asynchronous preset and clear

Examining behaviour of synthesis of flip-flops for the working module and module designed by the student as part of the experiment (refer to the circuit diagrams):

Many gate level flip-flop circuits such as JK flip-flop circuit with NAND implementation can not be simulated by the standard simulation algorithm, therefore, a special case analysis technique has been developed in order to support simulation. The simulator contains both behavioral and structural flip-flops. Behavioral flip-flops do not need any case analysis and race around condition does not occur in the JK behavioral flip-flop. To get a feel of real hardwares this experiment is designed based on the structural gate level flip-flops.

• Check set and reset properties of RS flip-flop by seting S = 1, R = 0 and S = 0, R = 1 respectively
• Simulate the JK flip-flop with NAND gate implementation without case analysis by seting J = 1, K = 0
• Simulate the JK flip-flop with NAND gate implementation with case analysis by seting J = 1, K = 0 and see the log to know how the unknown loops are resolved through case analysis (there is one backedge for each loop mentioned in the log)
• Check the behavior of D flip-flop by setting D = 1 or D = 0
• Check the race around condition of JK flip-flop at J = 1, K = 1
• Simulate the master slave JK flip-flop with case analysis. If if does not give valid output then the reason is inconsistent initialization (refer to theory)
• Simulate master slave JK flip-flop with asynchronous preset and clear without case analysis. First initialize the circuit with preset = 1, clear = 0 or preset = 0, clear = 1, then examine the avoidance of race around condition in master slave JK flip-flop at J = 1, K = 1

Recommended learning activities for the experiment: Leaning activities are designed in two stages, a basic stage and an advanced stage. Accomplishment of each stage can be self-evaluated through the given set of quiz questions consisting of multiple type and subjective type questions. In the basic stage, it is recommended to perform the experiment firstly, on the given encapsulated working module, secondly, on the module designed by the student, having gone through the theory, objective and procuder. By performing the experiment on the working module, students can only observe the input-output behavior. Where as, performing experiments on the designed module, students can do circuit analysis, error analysis in addition with the input-output behavior. It is recommended to perform the experiments following the given guideline to check behavior and test plans along with their own circuit analysis. Then students are recommended to move on to the advanced stage. The advanced stage includes the accomplishment of the given assignments which will provide deeper understanding of the topic with innovative circuit design experience. At any time, students can mature their knowledge base by further reading the references provided for the experiment.

Synthesis of flip-flops:

• Start the simulator as directed. For more detail please refer to the manual for using the simulator
• The simulator supports 5-valued logic
• To add the logic components to the editor or canvas (where you build the circuit) select any component and click on the position of the canvas where you want to add the component
• The pin configuration is shown when you select the component and press the 'show pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned component of palette
• To connect any two components select the connection tool of palette, and then click on the source terminal and then click on the the target terminal
• To move any component select the component using the selection tool and drag the component to the desired position
• To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a double click
• Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the output in digital format
• undo/redo, delete, zoom in/zoom out, and other functionalities have been given in the top toolbar for ease of circuit building
• Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can be set from the given 'set clock' button in the left toolbar
• Use 'plot graph' button to see input-output wave forms
• Users can save their circuits with .logic extension and reuse them
• After building the circuit press the simulate button in the top toolbar to get the output
• If the circuit contains a clock pulse input, then the 'start clock' button will start the simulation of the whole circuit. Then there is no need to again press the 'simulate' button
• If you are using linux platform then click on 'Linux(32 bit)' or if you are using then click on 'Windows(32 bit)'

Linux(32 bit)

Windows(32 bit)

Click here to download the older version of simulator

Click here to download the new version of simulator

OR

Launch the older version of Simulator

Launch the new version of Simulator

Once the simulator is downloaded, open the command prompt, then go to the directory where you have saved it using cd command and then give the following command to run the simulator:
java -jar coaSimulator.jar

Back

Back

Click here to download the older version of simulator

Click here to download the new version of simulator

OR

Launch the older version of Simulator

Launch the new version of Simulator

Once the simulator is downloaded, open the command prompt, then go to the directory where you have saved it using cd command and then give the following command to run the simulator:
java -jar Simulator.jar

Experiment-3 (Design of Registers and Counters) :

The web interface of the application is under development, so screenshots of the experiments are presented here.

This application is completely run under the platform independent editor frame.

As the clock input is under development, the complete simulation of registers and counters are not possible yet.

Screenshot of Experiment-3 (platform independent)

Synthesis of flip-flops:

References :

Books:

1. Digital Logic and Computer Design - M. Morris Mano. Pearson Education - Prentice Hall.
2. Digital Principles Foundation of Circuit Design and Application - Arun Kumar Singh. New Age Publishers.
3. The Art of Electronics - Paul Horowitz and Winfield Hill (1989). Cambridge University Press
4. Modern Dictionary of Electronics - Rudolf F. Graf (1999). Newnes

Web Sites:

• NPTEL (e-learning courses from IITs and IISC)

Virtual Lab is an initiative of Ministry of Human Resource and Development(MHRD) under National Mission of Education through ICT to provide an interactive environment over the internet for creating and conducting different laboratory experiments by sharing the costly equipments and the resources.

For more information about the Virtual Lab,please visit http://www.vlab.co.in/

Developers of Logic Design and Computer Organization Virtual Lab

• Dr. Chittaranjan Mandal
Professor, Computer Science & Engineering
Professor, Information Technology
IIT Kharagpur
• Gargi Roy
Senior Project Assistant
• Devleena Ghosh

Target Audience:

Under graduate students.

Courses Aligned With:

Computer organization and artitecture.

Pre-requisite Softwares:

• 32 bit java runtime environment and java 1.6 or above
• Recommended browser: mozilla firefox, google chrome

Feedback:

To give your feedback please visit the following link-

Sponsered by MHRD (NME-ICT) .

Tutorial on UI for lab:

Introduction:

1. The simulator contains a pallete on the right hand side. This pallete contains all the components and tools . Tools are used to act up on the components. Different tools:
   • Selection tool- used for selecting components
   • Marquee tool- used for selecting many components at a time by draggiung the mouse in the design area(editor).
   • Connection tool- used for connecting components
2. Components have been catagorized according to their functionality and put into different drawers in the pallete. The area under every drawer is scrallable, if you are unable to see all the components in a particular drawer just click on the area and scroll. Different drawers:
• Circuits- contains 8 and 16 terminal circuits and flow container which can hold other circuit components.
• Logic gates- contains all kinds of basic logic gates.
• Display and inputs- contains all kinds of component needed to give input to the circuit and displaying outputs of the circuit.
• Adders- contains different types of adder circuits.
• Sequential ckt- contains basic flip-flops for designing sequential circuits.
• Other Components- contains different kinds of components like decoders, multiplexers, arithmetic logic units(ALU), memory elements(RAM cell) required to design combinational circuits.
3. To add the components to the editor select any component(first click on the selection tool then click on the desired compoent) then finally click on the position of the editor window where you want to add the component.
4. The pin configuration of a component is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
5. To connect any two components select the Connection tool in the palette, and then click on the Source terminal and click on the target terminal(no drag and drop, simple click will serve the purpose). After the connection is over click the selection tool in the pallete.
6. To move any components select the Selection Mode and drag the component after selecting it.
7. If needed select any component in the editor while designing your circuit and use Undo, Redo, Delete, Zoom in, Zoom out buttons to get corresponding functionalities. Open and Save options are under development.
8. As the automated clock is under development and the simulator is under modification for sequencial circuits, for the time being please use individual clock(Bit switch which toggle its value with a double click) for each flip-flop.
9. The simulator is currently under modification for sequential circuits, now it is working properly for combinational circuits but may not give proper output for sequential circuits.

Description of Components:

1. Digital display: it can be used to give input and as well as to see the output in the decimal format, its right most terminal is the LSB(least significant bit) and the left most terminal is the MSB(most significant bit), in the editor after selecting a particular digital display you can use 'Increment LED' and 'Decrement LED' buttons in the top left corner of the simulator to increment and decrement its value respectively.
2. Bit display: it displays a single bit value.
3. V+: it gives 1 as input.
4. Ground: it gives 0 as input.
5. Bit switch: it gives 1/0 input, it toggels its value with a double click.

Testing process:

1. To test your circuit give some input(through Digital display or Bit switch or V+ or Ground), if you use the Digital display or Bit switch you can then give different input to you circuit through incrementing/decrementing the Digital display or double clicking the Bit switch, the other two gives constant inputs.
2. to see the output, connect Digital display or Bit display to the output terminals of your circuit.

Frequently Asked Questions:

What is virtual lab?

The Virtual Laboratory is an interactive environment for creating and conducting simulated experiments: a playground for experimentation. It consists of domain dependent simulation programs, experimental units called objects that encompass data files, tools that operate on these objects.

What are the advantages of virtual lab?

Virtual Logic Design and Computer Organisation lab enables students to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.

1. Digital Logic and Computer Organisation are core courses in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline ( Computer Science / Engg., Electronics, Electrical ] etc.
2. Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
3. Even when such FPGA boards are available, making them available round the clock is difficult.
4. Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
5. Helps to standardize the set of Experiments to a large extent.

What is eclipse platform?

Eclipse is a Java-based, extensible open source development platform. By itself, it is simply a framework and a set of services for building a development environment from plug-in components. Eclipse comes with a standard set of plug-ins, including the Java Development Tools (JDT).

Which framework is used to develop the application?

We have used the eclipse gef framework. The Graphical Editing Framework (GEF) allows developers to take an existing application model and quickly create a rich graphical editor.

What is platform independent application?

Applications that run under particular operating systems and/or particular hardwares are called platform dependent application whereas platform independent applications can run in any operating environment.

What are the experiments which can be performed by the Virtual Logic Design and Computer Organization lab?

The experiments that will be supported by this lab are given below:

1. Design of a ripple carry adder
2. Design of a carry-look-ahead adder
3. Design of registers and counters
4. Design of a wallace tree adder
5. Design of combinational multipliers
6. Design of a Booth’s multiplier
7. Design of an ALU
8. Design of memory units
9. Design of direct mapped cache
10. Design of associative cache
11. Design of combinational dividers
12. CPU design