Welcome to Logic Design and Computer Organization Virtual Lab
The Virtual Laboratory is an interactive environment for creating and conducting simulated experiments: a playground for experimentation. It consists of domain-dependent simulation programs, experimental units called objects that encompass data files, tools that operate on the objects.
The Objective is to Expose the students to the various key aspects of Digital Logic and Computer Organization by enabling them to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.
- Digital Logic and Computer Organization are core courses in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline(Computer Science / Engg., Electronics, Electrical) etc.
- Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
- Even when such FPGA boards are available, making them available round the clock is difficult.
- Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
- Helps to standardize the set of Experiments to a large extent.
Virtual Lab is an initiative of Ministry of Human Resource and Development(MHRD) under National Mission of Education through ICT to provide an interactive environment over the internet for creating and conducting different laboratory experiments by sharing the costly equipments and the resources.
For more information about the Virtual Lab,please visit:
Developers of Logic Design and Computer Organization Virtual Lab
- Dr C Mandal Professor, Computer Science & Engineering
- Parimal Santra Javascript Tool developer
- Gargi Roy Java Tool developer
- Devleena Ghosh Java Tool developer
IIT Kharagpur
Target audience:
Under graduate students.
Aligned courses:
Digital Logic and Computer organization.
Old java software:
- Java runtime environment is needed (may get from java.com)
- Recommended browsers: Mozilla Firefox, Google Chrome
- Download the 64-bit simulator for Linux
- If your environment is properly set up, you may open by double clicking on the jar file, otherwise use the following command: java -jar coldvl64LinuxSM.jar
- Download the 64-bit simulator for Windows
- PATH needs to be set:
- Right click on My Computer/This PC
- Select Properties
- Select Advanced System Settings
- Select Advanced tab
- Select Environment Variables
- Select Path under System Variables
- Click on Edit button
In Variable value editor paste this at the start of the line
C:\Program Files\Java\⟨jdk_version⟩\bin; - Click Ok then Ok again
- If your environment is properly set up, you may open by double clicking on the jar file, otherwise use the following command: java -jar coldvl64WindowsSM.jar needed
Workshop:
Download attendance form for students
Download attendance form for instructors
Objectives:
The Objective is to Expose the students to the various key aspects of Logic Design and Computer Organisation by enabling them to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.
- Digital Logic and Computer Organisation are core courses in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline(Computer Science / Engg., Electronics, Electrical) etc.
- Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
- Even when such FPGA boards are available, making them available round the clock is difficult.
- Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
- Helps to standardize the set of Experiments to a large extent.
Contact Information:
Mailing Address and Contact Information:Department of Computer Science & Engineering, IIT Kharagpur
Office : +91-3222-2882255
Postal Address:
Indian Institute of Technology Kharagpur, Kharagpur - 721302, INDIA Telephone Number +91-3222-255221 | FAX : +91-3222-255303
Tutorial on UI for lab:
Introduction:
- The simulator supports 5 valued logic. These 5 states along with their corresponding wire values are as follows:
- True(T) (wire color: blue)
- False(F) (wire color: black)
- High impedence(Z) (wire color: green)
- Unknown(X) (wire color: maroon)
- Invalid(I) (wire color: orange)
- The simulator contains a pallete on the right hand side. This pallete contains all the components and tools . Tools are used to act up on the components. Different tools:
- Selection tool- used for selecting components
- Marquee tool- used for selecting many components at a time by draggiung the mouse in the design area(editor).
- Connection tool- used for connecting components
- Components have been catagorized according to their functionality and put into different drawers in the pallete. The area under every drawer is scrallable, if you are unable to see all the components in a particular drawer just click on the area and scroll. Different drawers:
- Circuits- contains 8 and 16 terminal circuits and flow container which can hold other circuit components.
- Logic gates- contains all kinds of basic logic gates.
- Display and inputs- contains all kinds of component needed to give input to the circuit and displaying outputs of the circuit.
- Adders- contains different types of adder circuits.
- Sequential ckt- contains basic flipflops for designing sequential circuits.
- Other Components- contains different kinds of components like decoders, multiplexers, arithmetic logic units(ALU), memory elements(RAM cell) required to design combinational circuits.
- To add the components to the editor select any component(first click on the selection tool then click on the desired compoent) then finally click on the position of the editor window where you want to add the component.
- The pin configuration of a component is shown whenever the mouse is hovered on any canned component of the palette. Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise.
- To connect any two components select the Connection tool in the palette, and then click on the Source terminal and click on the target terminal(no drag and drop, simple click will serve the purpose). After the connection is over click the selection tool in the pallete.
- To move any components select the Selection Mode and drag the component after selecting it.
- If needed select any component in the editor while designing your circuit and use Undo, Redo, Delete, Zoom in, Zoom out buttons to get corresponding functionalities. Open and Save options are under development.
- As the automated clock is under development and the simulator is under modification for sequencial circuits, for the time being please use individual clock(Bit switch which toggle its value with a double click) for each flipflop.
Description of Components:
General components:- Digital display: it can be used to give input and as well as to see the output in the decimal format, its right most terminal is the LSB(least significant bit) and the left most terminal is the MSB(most significant bit), in the editor after selecting a particular digital display you can use 'Increment LED' and 'Decrement LED' buttons in the top left corner of the simulator to increment and decrement its value respectively.
- Bit display: it displays a single bit value.
- V+: it gives 1 as input.
- Ground: it gives 0 as input.
- Bit switch: it gives 1/0 input, it toggles its value with a double click.
Specific components:
Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases anticlockwise. Pin configurations of all the components-
- Half adder: i/p: 5,8 o/p: sum=4, carry=1
- Full adder: i/p: 5,6,8 o/p: sum=4, carry=1
- RCA 4 bit: (4 bit ripple carry adder) i/p: A0=13,A1=14,A2=15,A3=16; B0=17,B1=18,B2=19,B3=20; C0=21 o/p: S0=12,S1=11,S2=10,S3=9,Cout=8
- Wallace tree adder: (adds 3 4-bit numbers) i/p: A0=13,A1=14,A2=15,A3=16; B0=17,B1=18,B2=19,B3=20; C0=21,C1=22,C2=23,C3=24 o/p: S0=12,S1=11,S2=10,S3=9,Cout=8
- RS flipflop: i/p: R=5, S=8, Clk=7 o/p: Q=4, Q'=1
- D flipflop: i/p: D=5, Clk=8 o/p: Q=4, Q'=1
- T flipflop: i/p: T=8, Clk=7 o/p: Q=4, Q'=1
- JK flipflop: i/p: J=5, K=8, Clk=7 o/p: Q=4, Q'=1
- 2:4 Decoder: i/p: A0=5,A1=7 o/p: D0=4,D1=3,D2=2,d3=1
- 2:4 Decoder with enable: i/p: A=6,B=5, Enable=8 o/p: D0=4,D1=3,D2=2,d3=1
- 4:1 Mux: i/p: I0=9,I1=10,I2=11,I3=12,S0=13,S1=14 o/p: F=8
- Combinational Multiplier: i/p: multiplicand: A0=13,A1=14,A2=15,A3=16 Multiplier: B0=9,B1=10,B2=11,B3=12 o/p: S0=8,S1=7,S2=6,S3=5,S4=4,S5=3,S6=2,S7=1
- ALU 1 bit: i/p: A0=9, B0=10, C0=21 S0=12,S1=13 o/p: F=8, Cout=7
- 4 bit ALU: i/p: A0=13,A1=14,A2=15,A3=16; B0=17,B1=18,B2=19,B3=20; C0=21;S0=22,S1=23 o/p: F0=12,F1=11,F2=10,F3=9,Cout=8
- 16 bit ALU: i/p: A1=13,A2=15; B1=14,B2=16; Cin=9,S0=12,S1=11,S2=10 o/p: Cout=6,F2=7,F1=8
- RAM Cell: i/p=5, select=8, R/W'=6, o/p=4, R/W'=1 for read operation, R/W'=0 for write operation
- IC Memory: R/W'=16 Memory Enable=15, Address i/p=14,13 Data i/p=12,11,10 Data o/p=6,7,8 R/W'=1 for read operation, R/W'=0 for write operation
- Direct Mapped Cache:
- pin-32= S(selects whether user wants to perform cache write or cache mapping)
- pin-31= R/W'A(selects whether user wants to input the address or cache mapping)
- pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (thise 4 pins are used to give address input). A3 is the most significant bit and A0 is the least significant bit. A3 and A2 will be compared with the tag. A1 and A0 will select the corrsponding set.
- pin-26= R/W'D(selects whether user wants to input in the set of cache or cache mapping)
- pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the least significant bit). thiese two bits are used for cache writhe purpose, it selects the particular set of which user wants to give inputs to the valid bit, tag bits and data bits.
- pin-23= Den(this is an enable input which has to set for any write purpose in the cache).
- pin-21= valid bit
- pin-20= T1, pin-19=T0 (T1 is the most significant bit and T0 is the least significant bit). These are tag bits.
- pin-18= D1, pin-17=D0 (D1 is the most significant bit and D0 is the least significant bit). These are data bits.
- pin-14= Hit/Miss bit(if it gives 1 then hit otherwise miss)
- pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the least significant bit). These are output data bits and will be given only when there is a hit.
- Essential pin configurations for writing in cache: S=1, R/W'A=0, R/W'D=0, Den= 1
- Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1, Den= 0
Testing process:
- To test your circuit give some input(through Digital display or Bit switch or V+ or Ground), if you use the Digital display or Bit switch you can then give different input to you circuit through incrementing/decrementing the Digital display or double clicking the Bit switch, the other two gives constant inputs.
- to see the output, connect Digital display or Bit display to the output terminals of your circuit.
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Frequently Asked Questions:
What is virtual lab?
The Virtual Laboratory is an interactive environment for creating and conducting simulated experiments: a playground for experimentation. It consists of domain dependent simulation programs, experimental units called objects that encompass data files, tools that operate on these objects.
What are the advantages of virtual lab?
Virtual Logic Design and Computer Organisation lab enables students to perform FPGA based prototyping of experiments with support of a virtual environment. The primary need for virtualisation here is multifold.
- Digital Logic and Computer Organisation are core courses in most of the Undergraduate Curricula of the entire Electrical Sciences Discipline ( Computer Science / Engg., Electronics, Electrical ] etc.
- Many colleges/institutes cannot procure sufficient number of FPGA boards for their students.
- Even when such FPGA boards are available, making them available round the clock is difficult.
- Expert help is required to effectively use these FPGA boards and such help can be easily channeled through a virtual environment.
- Helps to standardize the set of Experiments to a large extent.
What is eclipse platform?
Eclipse is a Java-based, extensible open source development platform. By itself, it is simply a framework and a set of services for building a development environment from plug-in components. Eclipse comes with a standard set of plug-ins, including the Java Development Tools (JDT).
Which framework is used to develop the application?
We have used the eclipse gef framework. The Graphical Editing Framework (GEF) allows developers to take an existing application model and quickly create a rich graphical editor.
What is platform independent application?
Applications that run under particular operating systems and/or particular hardwares are called platform dependent application whereas platform independent applications can run in any operating environment.
What are the experiments which can be performed by the Virtual Logic design and Computer Organization lab?
The experiments that will be supported by this lab are given below:
- Design of a ripple carry adder
- Design of a carry-look-ahead adder
- Design of registers and counters
- Design of a wallace tree adder
- Design of combinational multipliers
- Design of a Booth’s multiplier
- Design of an ALU
- Design of memory units
- Design of direct mapped Cache
- Design of associative Cache
- Design of combinational dividers
- CPU design