Dr. Pallab Dasgupta
Professor,
Email: pallab[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Dr. Partha Pratim Chakrabarti
Professor,
Email: ppchak[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Dr. Soumyajit Dey
Assistant Professor,
Email: soumya[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Dr. Aritra Hazra
Assistant Professor,
Email: aritrah[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Sumana Ghosh
PhD, Formal Methods Laboratory
Email: sumanaghosh[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Rajorshee Raha
PhD, Formal Methods Laboratory,
Email: rajorshee[DOT]raha[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Antonio A. Bruto Da Costa
PhD, Formal Methods Laboratory
Email: bruto[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Rajib Lochan Jana
PhD, Formal Methods Laboratory
Email: jlrajib[DOT]cse[AT]gmail[DOT]com
Saurav Kumar Ghosh
PhD, Formal Methods Laboratory
Email: saurav{dot}kumar{dot}ghosh{at}cse{dot}iitkgp{dot}ernet{dot}in
Sudipa Mandal
PhD, Formal Methods Laboratory
Email: sudipa[DOT]mandal[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Thakkar Jay A.
PhD, Advanced Technology Development Centre
Formal Methods Laboratory
Email: jay1992[AT]atdc[DOT]iitkgp[DOT]ernet[DOT]in
Sayandeep Saha
PhD, Formal Methods Laboratory
Email: sahasayandeep[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in
Sayandeep Sanyal
PhD, Formal Methods Laboratory
Department of CSE
Email: sayandeep[DOT]sanyal[AT]gmail[DOT]com
Sunandan Adhikary
MS Student, Formal Methods Laboratory
Department of CSE
Email: mesunandan[AT]gmail[DOT]com
Dr. Antara Ain
Assertion Based Analysis of Mixed-Signal Systems
Email: antaraain[AT]gmail[DOT]com
Dr. Kamalesh Ghosh
Currently working in Synopsys
Automated Planning Based Methods for Early Verification of Reactive Control Systems
Dr. Aritra Hazra
Assistant Professor, IIT Kharagpur
Formal Methods for Architectural Power Intent Verification and Functional Reliability Analysis
Dr. Padmalochan Bera
Currently holding Faculty Position at IIT Bhubaneswar
Formal Analysis of Security Policy Implementations in Enterprise Networks
Dr. Priyankar Ghosh
Currently works in Synopsys India, Bangalore
Search Techniques for finding Alternative Solutions for AND/OR Graphs and Bi-objective Optimization Problems
Dr. Srobona Mitra
Currently Formal Verification Engineer at Synopsys India, Bangalore
Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated Circuits
Dr. Rajkumar P.V.
Currently Post Doc fellow at the Institute for Cyber Security, Univ of Texas, San Antonio, USA
Formal and Semi-Formal Methods for Application Specific Usage Control and Security
Dr. Subhankar Mukherjee
Currently with Mentor Graphics, Bangalore
Assertions - from a mixed-signal perspective
Dr. Manoj Dixit
Currently with Mathworks, Bangalore - formerly at GM India Science Labs
Formal Methods for Early Time-Budgeting in Component-based Embedded Control
Dr. Arijit Mondal
Currently holding Faculty Position at IIT Patna
A symbolic event propagation approach for solving timing problems of digital circuits
Dr. Bhaskar Pal
Currentlyworking for Synopsys in Formal Verification
Formal and semi-formal verification methods with constrained random test benches
Dr. Suchismita Roy
Currently holding Faculty Position at NIT Durgapur
SAT Based Solutions for Timing and Power Estimation in Gate Level Circuits
Dr. Ansuman Banerjee
Currently holding Faculty Position at ISI Kolkta
Formal Methods for accelerating formal, semi-formal and dynamic property verification through novel specification styles
Dr. Sayantan Das
Currently working for Verific/Electra Design Automation Pvt Ltd
Formal Analysis of Property Specifications: Consistency, Coverage and Synthesis
Dr. Prasenjit Basu
Currently working for Samsung Research, Bangalore
Design Intent Verification by Formal Property Coverage
Dr. Jatin K. Deka
Currently holding Faculty Position at IIT Guwahati
Model checking techniques for Reasoning about Events and Extremal Properties in Timed Systems