Reasoned Artificial Intelligence

• Learning Temporal Causal Sequence Relationships from Real-Time Time-Series.
  Antonio Anastasio Bruto da Costa, Pallab Dasgupta.
  Accepted for the publication in Journal of Artificial Intelligence Research (JAIR), October 2020 .

• Safety Augmentation in Decision Trees.
  Sumanta Dey, Pallab Dasgupta, Briti Gangopadhyay.
  Accepted for publication in IJCAI AI Safety Workshop 2020.


Identification of Test Cases for Automated Driving Systems Using Bayesian Optimization.
Briti Gangopadhyay, Siddartha Khastgir, Sumanta Dey, Pallab Dasgupta, Giovanni Montana, Paul Jennings.
Accepted in IEEE Intelligent Transportation Systems Conference (ITSC2019), Auckland, New Zealand, 2019

Modeling Formalisms for Design Verification

• A Fuzzy Real-Time Temporal Logic.
  Subhankar Mukherjee and Pallab Dasgupta.
  International Journal of Approximate Reasoning (Elsevier), 54(9), 1452-1470 (2013).


Some results on Parametric Temporal Logic.
M. Dixit, S.Ramesh and P. Dasgupta.
Information Processing Letters, 111(20): 994-998, 2011.


The Open Family of Temporal Logics: Annotating Temporal Operators with Input Constraints.
A. Banerjee and P. Dasgupta.
ACM Transactions on Design Automation and Embedded Systems (TODAES), 10 (3), 492-522, 2005.


The power of first-order quantification over states in branching and linear time temporal logics.
K. Chatterjee, P. Dasgupta, P.P. Chakrabarti.
Information Processing Letters, 91: 201-210, 2004.


A branching time temporal framework for Quantitative Reasoning.
K. Chatterjee, P. Dasgupta, P.P. Chakrabarti.
Journal of Automated Reasoning, 30: 205-232,2003.


Quantified Computation Tree Logic.
A.C.Patthak, I.Bhattacharya, A.Dasgupta, P.Dasgupta, P.P.Chakrabarti.
In Information Processing Letters, Feb 2002.


Min-max event triggered computation tree logic.
P. Dasgupta, P.P.Chakrabarti, J. K. Deka.
Sadhana, (Spl. Issue on Formal Verification), 27(2): 163-180,2002.


Min-max Computation Tree Logic.
P.Dasgupta, Jatindra K.Deka, P.P.Chakrabarti and S. Sriram.
Artificial Intelligence, Vol. 127(2001), 137-162.


Model checking on Timed Event Structures.
P.Dasgupta, Jatindra K. Deka and P.P.Chakrabarti.
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. 5, May 2000, 601-611.

Planning Based Guided Reconstruction of Corner Cases in Architectural Validation.
Rajib Lochan Jana, Shashank Kuchibhotla, Soumyajit Dey, Pallab Dasgupta.
In Proc. of 20th International Symposium of VLSI Design and Test (VDAT), May 2016.


On the realizability of specifications having auxiliary state machines and GR(1) LTL.
A. Banerjee, P.Dasgupta, P.P. Chakrabarti.
In Proc. of IEEE VDAT 2007.


Synthesis of System Verilog Assertions.
S.Das, R.Mohanty, P.Dasgupta and P.P.Chakrabarti.
DATE-06, Munich, Germany, 2006.


Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures.
K. Chatterjee, P.Dasgupta, and P.P.Chakrabarti.
In Proceedings of IWDC, 2004 (102-113).


An Assertion-based Language for Generating Test Sequences for Complex Temporal Behavior.
P. Roy, P. Dasgupta, P.P. Chakrabarti.
In VDAT, 2004.


Open Computation Tree Logic With Fairness.
A. Banerjee, P. Dasgupta, P.P. Chakrabarti.
In Proc. of IEEE International Symposium on Circuits and Systems (ISCAS) 2003, Bangkok 2003.


Open Computation Tree Logic for Formal Verification of Modules.
P.Dasgupta, A. Chakrabarti, P.P.Chakrabarti.
In Proc. of ASPDAC / VLSI Design 2002: ACM/IEEE Joint Conference of Asia Pacific Design Automation Conference and VLSI Design Conference, 2002.


Abstraction of word-level linear arithmetic functions from bit-level component descriptions.
P.Dasgupta, P.P. Chakrabarti, Amit Nandi, Sekar Krishna and Arindam Chakrabarti.
In Proc. of Design Automation and Test in Europe (DATE), Munich, Germany, 2001.


Weighted Quantified Computation Tree Logic.
K. Chatterjee, P.Dasgupta and P.P.Chakrabarti.
In Proc. of CIT-01: International Conf. On Information Technology, India 2001.


Specification of Planning Goals in Branching Time Logics in Stochastic Systems.
Sudeshna Sarkar, P.P.Chakrabarti, Rajdeep Niyogi and P.Dasgupta.
In Proc. of KBCS-2000, Int. Conf. on Knowledge Based Computer Systems, 2000.

• Automated Planning for finding Alternative Bug Traces.
  Rajib Lochan Jana, Soumyajit Dey, Pallab Dasgupta, Arijit Mondal.
  IET Computers & Digital Techniques (Accepted), 2020.


• Formal Guarantees for Localized Bug Fixes.
  Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta, Priyankar Ghosh, Harish Kumar.
  IEEE Transactions on CAD of Integrated Circuits and Systems 32(8): 1274-1287 (2013).


Counterexample Ranking Using Mined Invariants.
Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta and Harish Kumar.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sytems, 32(12), 1978-1991, 2013.


Early analysis of critical faults: An approach to test generation from formal specifications.
S. Das, A. Banerjee and P. Dasgupta.
IEEE Transactions on CAD (TCAD), 31(3):447-451,March 2012..


Verification by parts: Reusing component invariant checking results.
S. Mitra, P. Ghosh and P. Dasgupta.
IET Computers and Digital Techniques, 6(1): 19-32,Jan 2012.


Cohesive Coverage Management: Simulation Meets Formal Methods.
Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta and P. P. Chakrabarti.
Journal of Electronic Testing: Theory and Applications (JETTA), vol. 28, no. 4, pp. 449-468, 2012.


Design Intent Coverage Revisited.
Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P.P. Chakrabarti.
ACM Transactions on Design Automation of Electronic Systems, 14 (1)2009, 9:1-9:32.


Auxiliary state machines + context triggered properties in verification.
Ansuman Banerjee, Pallab Dasgupta, P.P. Chakrabarti.
ACM Transactions on Design Automation of Electronic Systems, 13 (4), 2008, 62:1-62:31.


Accelerating Assertion Coverage with Adaptive Test-benches.
Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta.
IEEE Transactions on CAD (TCAD), Volume 27, Issue 5, Pages:967 - 972,May 2008.


BUSpec: A framework for generation of verification aids for Standard Bus Protocol Specifications.
B.Pal, A.Banerjee, P. Dasgupta, and P.P. Chakrabarti.
Integration - the VLSI Journal, Elsevier, Vol 40, I3, pp. 285-304,2007.


Hardware Accelerated Constrained Random Test Generation.
Bhaskar Pal, Arnab Sinha, P. Dasgupta, P.P. Chakrabarti, Kaushik De.
IET Computers and Digital Techniques, vol. 1, no. 4, 423-433,2007.


Design Intent Coverage - A New Paradigm for Formal Property Verification.
P.Basu, S.Das, A.Banerjee, P. Dasgupta, P.P. Chakrabarti, C.R. Mohan, L.Fix, R.Armoni.
IEEE Transactions on CAD, 25 (10) 1922-1934, 2006.

Acceptance and Random Generation of Event Sequences under Real Time Calculus constraints.
Kajori Banerjee, Pallab Dasgupta.
In Proc of of Design Automation and Test in Europe (DATE), Dresden, 2014.


Debugging Assertion Failures in Software Controllers using a Reference Model.
Kajori Banerjee, Santhosh Prabhu M and Pallab Dasgupta.
In Proc. of 6th India Software Engineering Conference (ISEC), 2013.


A Generalized Theory for Formal Assertion Coverage.
Sourasis Das, Ansuman Banerjee and Pallab Dasgupta.
IEEE Asian Test Symposium (ATS), 137-142, 2012.


Formal Methods for Ranking Counterexamples Through Assumption Mining.
Srobona Mitra, Ansuman Banerjee and Pallab Dasgupta.
In Proc. of Design Automation and Test in Europe (DATE), Dresden, 2012.


Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces.
Anvesh Komuravelli, Srobona Mitra, Ansuman Banerjee and Pallab Dasgupta.
In Proceedings of Asian Test Symposium (ATS), pp. 238-243, November 2011.


A Study of Modeling Techniques in use in Digital and Mixed-Signal Domains for Semi-Formal Verification.
Srobona Mitra, Antara Ain, Priyankar Ghosh and Pallab Dasgupta.
In the Proceedings of IEEE TechSym, April 2010.


Coverage Management with Inline Assertions and Formal Test Points.
Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, P. P. Chakrabarti.
In the proceedings of VLSI Design Conference 2010.


Directed Automated Symbolic Verification Of Formal Properties With Local Variables.
Sourasis Das, Pallab Dasgupta, Ansuman Banerjee, P. P. Das.
In IEEE TENCON Conference, November 2009.


Abstraction Refinement for State Space Partitioning based on Auxiliary State Machines.
Priyankar Ghosh, B. Ramesh, Ansuman Banerjee, Pallab Dasgupta.
In IEEE TENCON Conference, November 2009.


Incremental Verification Techniques for an Updated Architectural Specification.
Srobona Mitra, Priyankar Ghosh, Pallab Dasgupta, P. P. Chakrabarti.
In INDICON Conference, December 2009.


Inline Assertions - Embedding Formal Properties in a Test Bench.
Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, P.P. Chakrabarti.
In VLSI Design, Delhi, India, , IEEE (2009) .


Dynamic Assertion-based Verification Platform for UML Statecharts over Rhapsody.
Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P.P. Chakrabarti, S. Ramesh, P.V.V. Ganesan.
Lecture Notes in Computer Science, Sringer Verlag, Vol 5311, 222-227, In Proc. of Advanced Technology for Verification and Analysis (ATVA), Seoul, Korea, (2008).


CheckSpec: A Tool for Consistency and Coverage Analysis of Assertion Specifications.
Ansuman Banerjee, K. Datta, Pallab Dasgupta.
Lecture Notes in Computer Science, Sringer Verlag, Vol 5311, 228-233, In Proc. of Advanced Technology fo Verification and Analysis (ATVA), Seoul, Korea, (2008).


Debugging Assume-Guarantee Specifications for Compositional Verification.
A. Nandi, B. Pal, P.Dasgupta.
In Proc. of IEEE VDAT, 2007.


A Debugging Utility for Assertion-based Protocol Verification.
B.Pal, A.Nandi, P.Dasgupta, P.P. Chakrabarti.
In Proc. of EAIT, 2006.


Property Driven Test Generation in Absence of Direct Interface.
Bhaskar Pal, P. Dasgupta, Partha P. Chakrabarti.
In Proc. of IEEE INDICON 2006, Sept. 15-17, 2006, New Delhi, India.


Automatic Test Generation for Temporal Coverage Points using a Stochastic Tree Model.
A. Nandi, B.Pal, P.Dasgupta, P.P. Chakrabarti.
In Proc. of VDAT 2006.


Discovering input assumptions in specification refinement coverage.
P.Basu, S.Das, P.Dasgupta, and P.P. Chakrabarti.
In ASPDAC-06, Yokohama, Japan, 2006.


What lies between Design Intent Coverage and Model checking?
S.Das, P.Basu, P.Dasgupta, P.P. Chakrabarti.
In DATE -06, Munich, Germany, 2006.


Test Generation Games from Formal Specifications.
A. Banerjee, B.Pal, S.Das, A. Kumar, P.Dasgupta.
In Proc. of Design Automation Conference (DAC), San Francisco, 2006.


Test Plan Coverage by Formal Property Verification.
P. Basu, S. Das, A. Banerjee, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of VDAT 2005.


H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions.
A. Nandi, B. Pal, N. Chhetan, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of INDICON, 2005.


Interactive Test-Bench Synthesis for Assertion-Based Verification.
A. Banerjee, S. Chakravorty, B. Pal, P. Dasgupta.
In Proceedings of INDICON, 2005.


Scoreboard Directed Dynamic Constraint Modification for Higher Simulation Coverage.
B. Pal, A. Nandi, S. Ray, A. Banerjee, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of SNUG, 2005.


Syntax-driven Approximate Coverage Analysis for an Assertion Suite against a High-Level Fault Model.
S. Das, P. Basu, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of VDAT 2005.


Bounded Model Checking for OpenLTL.
S. Roy, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of VDAT 2005.


SAT based solutions for Consistency Problems in Formal Property Specifications for Open Systems.
S. Roy, S. Das, P. Basu, P. Dasgupta, P.P. Chakrabarti.
In ICCAD-05, San Jose, California, 2005.


Syntactic Transformation of Assume-Guarantee Assertions: From Sub-modules to Modules.
P. Basu, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of VLSI, 2005.


Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.
S. Das, A. Banerjee, P. Basu, P. Dasgupta, P.P. Chakrabarti, C.R. Mohan, L. Fix.
In Proceedings of VLSI, 2005.


Assertion-based Verification: Have I written Enough Properties?
A. Banerjee, B. Pal, K.Chaitanya, P. Dasgupta, P.P. Chakrabarti.
In IEEE INDICON 2004.


The BUSpec Platform for Automated Generation of Verification Aids for Standard Bus Protocols.
B. Pal, A. Banerjee, P. Dasgupta, P.P. Chakrabarti.
In MEMOCODE 2004, San Diego, California.


Design Issues for Assertion-Based Verification IPs: The OVA Experience.
A. Banerjee, B. Pal, P. Dasgupta, P.P. Chakrabarti, M. Jha. E. Cerny.
In SNUG 2004, Bangalore, India.


A Simulation Coverage Metric for Analyzing the Behavioral Coverage of an Assertion Based Verification IP.
B.Pal, A.Banerjee, K.Chaitanya, P. Dasgupta, P.P. Chakrabarti.
In VDAT, 2004.


Formal Verification Coverage: Are the RTL Properties Covering the Design's Architectural Intent?
P. Basu, S. Das, P. Dasgupta, P.P. Chakrabarti, C.R. Mohan.
In DATE 2004, Paris.


Formal Verification Coverage: Computing the Coverage Gap between Temporal Specifications.
S. Das, P. Basu, A. Banerjee, P. Dasgupta, P.P. Chakrabarti, C.R. Mohan. L. Fix, R. Armoni.
In ICCAD-04, San Jose, California, 2004.


Formal Verification of Modules under Real Time Environment Constraints.
A. Banerjee, P. Dasgupta, P.P. Chakrabarti.
In Proceedings of VLSI, 2004.


Property Refinement Techniques for Enhancing Coverage of Formal Property Verification.
P. Basu, P. Dasgupta, P.P. Chakrabarti, Chunduri R.
In Proceedings of VLSI, 2004.


Formal Verification of Module Interfaces against Real Time Specifications.
A. Chakrabarti, P.Dasgupta, P.P.Chakrabarti and A. Banerjee.
In Proc. of Design Automation Conference (DAC),New Orleans, 2002.


Symbolic verification of boolean constraints over partially specified functions.
S. Sriram, R. Tandon, P.Dasgupta and P.P.Chakrabarti.
IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australia, 2001.


Verification of Concurrent Communicating Systems in Boolean SDL.
A.C. Patthak, I. Bhattacharya, A. Dasgupta, P.P. Chakrabarti and P.Dasgupta.
In Proc. of Intell. Comput and VLSI, 2001.


An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays.
J.K.Deka, P.Dasgupta and P.P.Chakrabarti.
In Proc. of IEEE VLSI Design'99, 1999, 294-299.


Exploiting isomorphism for compaction and faster simulation of binary decision diagrams.
Pankaj Chauhan, P.Dasgupta and P.P.Chakrabarti.
In Proc. of IEEE VLSI Design'99, 1999.


Controlling State Explosion in Static Simulation by Selective Composition.
P.P.Chakrabarti, P.Dasgupta, P.P.Das, Arnob Roy, Shuvendu Lahiri, and Mrinal Bose.
In Proc. of VLSI Design'99, ACM/IEEE Int. Conf. on VLSI Design, 1999, 226-231.

Usage-driven Personalization of Power Management Logic
Sudipa Mandal, Aritra Hazra, Pallab Dasgupta
Accepted in IEEE Embedded System Letters (ESL), July 2020, DOI:10.1109/LES.2020.3010368.


• Formal Hardware/Software Co-Verification of Embedded Power Controllers
  Pallab Dasgupta, M.K. Srivas, Rajdeep Mukherjee
  IEEE Transactions on CAD of Integrated Circuits and Systems, 33(12), 2025-2029 (2014)


A Multi-Objective Perspective for Operator Scheduling using Fine-Grained DVS Architectures.
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta and Ajit Pal.
International journal of VLSI design and Communication Systems (VLSICS), 4(1), 105-122, 2013.


POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.
Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee and Subhankar Mukherjee.
IEEE Trans. on CAD of Integrated Circuits and Systems 32(11): 1801-1813, 2013.


An Integrated Approach for Fine-Grained Power and Temperature Management During High-level Synthesis.
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta and Ajit Pal.
Journal of Low Power Electronics (JOLPE), 9(3), 350-362, 2013.


Formal Verification of Architectural Power Intent.
Aritra Hazra, Sahil Goyal, Pallab Dasgupta and Ajit Pal.
IEEE Transaction on VLSI Systems (TVLSI), vol. 21, no. 3, pp. 78-91, 2013.


Symbolic event propagation based minimal test set generation for robust path delay faults.
A.Mondal, P.P. Chakrabarti and P. Dasgupta.
ACM Transactions on Design Automation of Electronic Systems, vol. 17 (4), 2012.


SAT based timing analysis for fixed and rise/fall gate delay models.
S. Roy, P.P. Chakrabarti and P. Dasgupta.
Integration VLSI J, Elsevier, 40(4), 357-364, 2012.


Power-SIM: An SOC simulator for estimating power profiles of mobile workloads.
P. Ghosh, A. Hazra, R. Gonnabhaktula, N. Bhilegaonkar, P. Dasgupta, C.R. Mandal and K. Paul.
Journal of Low Power Electronics, vol. 8, no. 3, pp. 293-303, 2012.


Bounded Delay Timing Analysis and Power Estimation using SAT.
Suchismita Roy, P.P. Chakrabarti and P. Dasgupta. Microelectronics Journal, 41(5), May 2010, 317-324.


Satisfiability Models for Maximum Transition Power.
S.Roy, P.P.Chakrabarti, Pallab Dasgupta.
IEEE Transactions on VLSI Systems, 16 (8), 2008 941-951.


Event propagation for accurate circuit delay calculating using SAT.
Suchismita Roy, P. Dasgupta, P.P. Chakrabarti.
ACM Transactions on Design Automation of Electronic Systems, 12(3), 2007, 36:1-36:23.


Statistical Timing Analysis using Symbolic Event Propagation.
A.Mondal, P.P.Chakrabarti, P.Dasgupta.
IET Circuits, Devices & Systems, 1(4), 2007, 283-291.

Model Checking of Global Power Management Strategies in Software with Temporal Logic Properties.
Rajdeep Mukherjee, Subhankar Mukherjee and Pallab Dasgupta.
In Proc. of 6th India Software Engineering Conference (ISEC), 2013.


Formal Verification of Hardware/Software Power Management Strategies.
Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal and Subhankar Mukherjee.
In Proc. of IEEE VLSI Design Conference, 2013.


Multi-Objective Low-power CDFG Scheduling using Fine-Grained DVS Architecture in Distributed Framework.
Rajdeep Mukherjee, Priyankar Ghosh, Neerati Sravan Kumar, Pallab Dasgupta and Ajit Pal.
International Symposium on Electronic System Design (ISED), pp. 267 - 271, 2012.


Operator Scheduling Revisited : A Multi-Objective Perspective for Fine-Grained DVS Architecture.
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta and Ajit Pal.
In the 2nd International Conference on Advances in Computing and Information Technology (ACITY), pp. 633-648, 2012.


Workload Driven Power Domain Partitioning.
Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta and Chittaranjan Mandal.
In VLSI Design and Test (VDAT) Conference, pp. 147 - 155, 2012.


Formal Methods for Coverage Analysis of Architectural Power States in Power-Managed Designs.
Aritra Hazra, Pallab Dasgupta, Ansuman Banerjee and Kevin Harer.
In Proc. of 17th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 585-590, Sydney, January 2012.


POWER-SIM : An SOC Simulator for Estimating Power Profiles of Mobile Workloads.
Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan Mandal and Krishna Paul.
In Proc. of International Symposium on Electronic System Design (ISED), pp.273-278, December 2011.


Leveraging UPF-Extracted Assertions for Modeling and Formal Verification of Architectural Power Intent.
Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi and Kaustav Guha.
In the Proceedings of Design Automation Conference (DAC), June 2010, Anaheim, California, USA.


Accelerating Synchronous Sequential Circuits using an Adaptive Clock.
Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta.
In the proceedings of VLSI Design Conference 2010.


Timing analysis of sequential circuits using symbolic event propagation.
Arijit Mondal, P.Dasgupta, P.P. Chakrabarti.
In Proc. of International Conference on Computing: Theory and Applications, Platinum Jubilee conference of ISI Kolkata, 2007.


A New Pseudo-Boolean Satisfiability based Approach to Power Mode Schedulabity Analysis.
Sayak Ray, P.Dasgupta, P.P. Chakrabarti.
In Proc. of VLSI Design, 2007.


Bounded Delay Timing Analysis using Boolean Satisfiability.
Suchismita Roy, P.P. Chakrabarti, P.Dasgupta.
In Proc. of VLSI Design, 2007.


A framework for estimating peak power in gate-level circuits.
D.Chakraborty, P.P. Chakrabarti, A. Mondal, and P.Dasgupta.
In International workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier,France, 2006.


Exact method for estimating Expected Settling Power in Sequential Circuits.
D. Chakraborty, P.P. Chakrabarti, P.Dasgupta.
In Proc. of VDAT 2006.


Formal Verification of Power Scheduling Policies for Battery Powered Mobile Systems.
Sayak Ray, P.Dasgupta, P.P. Chakrabarti.
In Proc. of IEEE INDICON 2006, Sept. 15-17, 2006, New Delhi, India.


Abstractions for Model Checking of Event Timings.
Jatindra K. Deka, S. Chaki, P.Dasgupta and P.P.Chakrabarti.
IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australia, 2001.

Recurrence in Dense-time AMS Assertions.
Sayandeep Sanyal, Antonio Anastasio Bruto da Costa, Pallab Dasgupta.
Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.


A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits.
Sayandeep Sanyal, Mayukh Bhattacharya, Amit Patra, Pallab Dasgupta.
Accepted for publication in Journal of Electronic Testing: Theory and Applications (JETTA), 2020.


Assertions for Protecting Mixed-Signal Latency Contracts in Power Management.
Sudipa Mandal, Pallab Dasgupta, Aritra Hazra, Chunduri Rama Mohan.
Accepted in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), July 2020, DOI: 10.1109/TVLSI.2020.3002481.


Formal Feature Interpretation of Hybrid Systems
Antonio A. Bruto da Costa, Goran Frehse, Pallab Dasgupta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, TCAD, 2018.


Interpreting Local Variables in AMS Assertions during Simulation
Antara Ain, Pallab Dasgupta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, TCAD, 2018.


• Feature Indented Assertions for Analog and Mixed-Signal Validation
  Antara Ain, Antonio A Bruto Da Costa, Pallab Dasgupta
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 11, pp. 1928-1941, Nov. 2016.


Formal Interpretation of Assertion Based Features on AMS Designs
Antonio A Bruto Da Costa, Pallab Dasgupta
IEEE Design and Test, 32(1), 9-17, (2015)


Post-Silicon Debugging of PMU Integration Errors using Behavioral Models.
Antara Ain, Subhankar Mukherjee, P. Dasgupta, S. Mukhopadhyay.
Integration - the VLSI Journal, Elsevier, 46(3), 310-321, 2013.


Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice.
Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay, Scott Little, John Havlicek, Srikanth Chandrasekaran.
ACM Trans. Design Autom. Electr. Syst. 17(4): 38 (2012).


Assertion Aware Sampling Refinement: A Mixed-Signal Perspective.
Subhankar Mukherjee, Pallab Dasgupta.
IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1772-1776 (2012).


Computing Minimal Debugging Windows in Failure Traces of AMS Assertions.
Subhankar Mukherjee, Pallab Dasgupta.
IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1776-1781 (2012).


Chassis: A Platform for Verifying PMU Integration using Auto-Generated Behavioral Models.
Antara Ain, Debjit Pal, Pallab Dasgupta, S. Mukhopadhyay, R. Mukhopadhyay, John Gough.
ACM Transactions on Design Automation of Electronic Systems, 16(3), June 2011.


Auxiliary Specifications for Context-Sensitive Monitoring of AMS assertions.
Subhankar Mukherjee, P. Dasgupta, S. Mukhopadhyay.
IEEE Transactions on CAD (TCAD), 30(10): 1446-1457, 2011.


A static verification approach for architectural integration of mixed-signal integrated circuits.
Rajdeep Mukhopadhyay, Anvesh Komuravelli, Pallab Dasgupta, Subrat K. Panda, Siddhartha Mukhopadhyay.
Integration - the VLSI Journal, Elsevier Pub., 43(1), Jan 2010, 58-71.


Instrumenting AMS Assertion Verification on Commercial Platforms.
Rajdeep Mukhopadhyay, S K Panda, Pallab Dasgupta, John Gough.
ACM Transactions on Design Automation of Electronic Systems, 14 (2), 2009, 21:1-21:47.

• Fault Vulnerability Ranking of Transistors in Analog Integrated Circuits using AC Analysis
  Shan Pavan Pani Krishna Garapati, Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya
  Accepted for Publication in International Test Conference India 2020, Bangalore, India.


• CoveRT: A Coverage Reporting Tool for AMS Designs.
  Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, and Lakshmanan Balasubramanian.
  33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), Bangalore, India, 2020, pp. 119-124, doi: 10.1109/VLSID49098.2020.00038


The Notion of Cross Coverage in AMS Design Verification.
Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, and Lakshmanan Balasubramanian.
25th Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, 2020, pp. 217-222, doi: 10.1109/ASP-DAC47756.2020.9045131.


A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits.
Sayandeep Sanyal, Amit Patra, Pallab Dasgupta, Mayukh Bhattacharya.
28th IEEE Asian Test Symposium (ATS), Kolkata, India, 2019, pp. 135-1355, doi: 10.1109/ATS47505.2019.00025.


Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis
Sayandeep Sanyal, Shan Pavan Pani Krishna Garapati, Amit Patra, Pallab Dasgupta,Mayukh Bhattacharya
In Proceedings of the 2019 on Great Lakes Symposium on VLSI, Washington DC, USA, pp. 123-128, 2019


• Feature Based Coverage Analysis of AMS Circuits
  Antara Ain, Akshay Mambakam, and Pallab Dasgupta
  In Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, July 2018.


AMS-Miner: Mining AMS Assertions using Interval Arithmetic
Antonio Anastasio Bruto da Costa, Shriya Dharade, Sudipa Mandal and Pallab Dasgupta
In Proceeding of VLSID 2018, Pgs 404-409.


Formal Methods for Coverage Analysis of Power Management Logic with Mixed-Signal Components
Sudipa Mandal, Aritra Hazra, Pallab Dasgupta, and R. M. Chunduri
In Proceeding of VLSID 2018, Pgs 37-42.


A Machine Learning Approach for Choosing Component Level Conditions for Prognostics of AMS Systems
Sayandeep Sanyal, Antara Ain and Pallab Dasgupta
IEEE International Symposium on Devices, Circuits and Systems (ISDCS), Howrah, 2018, pp. 1-6, doi: 10.1109/ISDCS.2018.8379641.


ForFET: A Formal Feature Evaluation Tool for Hybrid Systems (Tool Paper)
Antonio Anastasio Bruto da Costa, Pallab Dasgupta
In Proc. of ATVA, October 2017


A Framework for Automated Feature Based Mixed-Signal Equivalence Checking
Antara Ain, Sayandeep Sanyal, Pallab Dasgupta
In International Symposium on VLSI Design and Test, PP. 779-791, Springer, Singapore, 2017


Generating AMS Behavioral Models with Formal Guarantees on Feature Accuracy.
Antonio Anastasio Bruto da Costa, Pallab Dasgupta
VLSI Design 2017: 233-238


Formal Verification of Power Management Logic with Mixed-Signal Domains.
Sudipa Mandal, Antonio Anastasio Bruto da Costa, Aritra Hazra, Pallab Dasgupta, Bhushan Naware, Chunduri Rama Mohan, Sanjib Basu.
VLSI Design 2017: 239-244


Formal feature analysis of hybrid automata
Antonio Anastasio Bruto da Costa, Pallab Dasgupta, Goran Frehse
In proceedings of MEMOCODE 2016: 2-11.


Monitoring AMS Simulation: From Assertions to Features
Antara Ain, Pallab Dasgupta
IEEE VLSI Design Conference, 429-434, Bangalore (2015)


A Library for Passive Online Verification of Analog and Mixed-Signal Circuits.
Debjit Pal, Pallab Dasgupta and Siddhartha Mukhopadhyay.
In Proc. of IEEE VLSI Design Conference, pp. 364-369, January 2012.


Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions.
Subhankar Mukherjee and Pallab Dasgupta.
In the proceedings of VLSI Design Conference 2011.


Auto-Generation of AMS Behavioral Models in Different Languages from Hybrid Automata.
Antara Ain and Pallab Dasgupta.
In the Proceedings of IEEE TechSym, April 2010.


Incorporating Local Variables in Mixed-Signal Assertions.
Subhankar Mukherjee, Pallab Dasgupta.
In IEEE TENCON Conference, November 2009.


Assertion-Based Verification of Mixed-Signal Behaviors with Sampling Clock.
Subhankar Mukherjee, Subrat K. Panda, Pallab Dasgupta.
In the proceedings of SNUG India 2009.


A Formal Approach for Specification-Driven AMS Behavioral Model Generation.
Subhankar Mukherjee, Antara Ain, Subrat K. Panda, Rajdeep Mukhopadhyay, Pallab Dasgupta.
In the proceedings of DATE 2009, Nice, France.

• SMT-based Verification of Safety-Critical Embedded Control Software.
  Sunandan Adhikary, Amit Gurung, Jay Thakkar, Antonio Bruto Da Costa, Soumyajit Dey, Aritra Hazra, Pallab Dasgupta.
  Accepted for the publication in IEEE Embedded Systems Letters (ESL), 2020 .


Performance-driven Post Processing of Control Loop Execution Schedules.
Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta.
Accepted for the publication in ACM Transaction on Design Automation of Electronic Systems (TODAES), 2020 .


A Hierarchical HVAC Control Scheme for Energy-Aware Smart Building Automation.
Rajib Lochan Jana, Soumyajit Dey, Pallab Dasgupta.
ACM Transactions on Design Automation of Electronic Systems, Vol. 25, Issue 4, May 2020.


Pattern Guided Integrated Scheduling and Routing in Multi-hop Control Networks
Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta
ACM Transaction on Embedded Computing Systems (ACM-TECS), Volume:19, No: 2, Article: 9, Feb 2020, DOI : 10.1145/3372134.


• Performance and Energy Aware Robust Specification of Control Execution Patterns under Dropped Samples
  Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta
  IET Computers & Digital Techniques (CDT), Volume: 13, Issue: 6, pp: 493–504(11), Nov, 2019, DOI: 10.1049/iet- cdt.2019.0030.


Algorithmic Approaches for optimizing Electronic Control Unit time using Multi-rate Sampling
Rajorshee Raha, Soumyajit Dey and Pallab Dasgupta
Journal of Control Theory and Technology, 16(3), 173-190, Springer, 2018


Co-synthesis of Loop Execution Patterns for Multi-Hop Control Networks
Sumana Ghosh, Soumyajit Dey and Pallab Dasgupta
IEEE Embedded System Letters (ESL), Volume: 10, Issue 4, pp 111-114, Dec. 2018, DOI: 10.1109/LES.2017.2777506.


A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control
Sumana Ghosh, Souradeep Dutta, Soumyajit Dey and Pallab Dasgupta
ACM Trans. Embed. Comput. Syst., 16(5s):189:1–189:22, Sept. 2017


• Formal Methods for Validation and Test Point Prioritization in Railway Signaling Logic
  Shiladitya Ghosh, Arindam Das, Nirvik Basak, Pallab Dasgupta, Alok Katiyar
  IEEE Trans. Intelligent Transportation Systems, 18(3): 678-689 (2017)


Multi-rate Sampling for Power-Performance Tradeoff in Embedded Control
Rajorshee Raha, Souradeep Dutta, Soumyajit Dey, Pallab Dasgupta
IEEE Embedded Systems Letters 8(4): 77-80 (2016)


Formal Assessment of Reliability Specifications in Embedded Cyber-Physical Systems
Aritra Hazra, Palab Dasgupta and Partha Pratim Chakrabarti
Journal of Applied Logic (JAL), Elsevier, 18: 71-104, 2016


Automated Planning as an Early Verification Tool for Distributed Control
Kamalesh Ghosh, Pallab Dasgupta and S. Ramesh
Journal of Automated Reasoning, 54(1), 31-68 (2015)


Time-Budgeting: A Component Based Development Methodology for Real-time Embedded Systems.
Manoj Dixit, S.Ramesh and Pallab Dasgupta.
Formal Aspects of Computing (FAOC), Springer, 26(3), 591-621, 2014.


Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications.
Aritra Hazra, Priyankar Ghosh, Satya Gautam Vadlamudi, P. P. Chakrabarti, Pallab Dasgupta.
Embedded Systems Letters 5(1): 8-11 (2013).


Reliability Guarantees in Automata Based Scheduling for Embedded Control Software.
Santhosh Prabhu M, Aritra Hazra and Pallab Dasgupta.
IEEE Embedded Systems Letters (ESL), vol. 5, no. 2, pp. 17-20, 2013.


A dynamic assertion-based verification platform for validation of UML designs.
A. Banerjee, Sayak Ray, P. Dasgupta, P. P. Chakrabarti, S. Ramesh, P. V. V. Ganesan.
ACM SIGSOFT Software Engineering Notes 37(1), 2012, 1-14.

Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples
Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta
International Conference on VLSI Design (VLSID), pages 1-6, Jan. 2019, DOI:10.1109/VLSID.2019.00019.


• Scheduling of Controllers' Update-rates for Residual Bandwidth Utilization
  Majid Zamani, Soumyajit Dey, Sajid Mohamed, Pallab Dasgupta and Manuel Mazo Jr.
  FORMATS 2016.


Formal Verification of Movement Authorities in Automatic Train Control Systems
Shiladitya Ghosh, Pallab Dasgupta, Chittaranjan Mandal, Alok Katiyar
In proceedings of the IET International Conference on Railway Engineering, 2016.


Adaptive Sharing of Sampling Rates among Software Based Controllers
Rajorshee Raha, Soumyajit Dey, Pallab Dasgupta
IEEE Multiconference on Systems and Control (MSC), Sydney, 2015


Formal Methods for Pattern Based Reliability Analysis in Embedded Systems
Sumana Ghosh, Pallab Dasgupta
IEEE VLSI Design Conference, Bangalore, (2015)


Synthesis of Sampling Modes for Adaptive Control
Rajorshee Raha, Aritra Hazra, Akash Mondal, Soumyajit Dey, Partha Pratim Chakrabarti, Pallab Dasgupta
IEEE International Conference on Control System, Computing and Engineering, Penang, Malaysia, (2014).


Multi-mode Sampling Period Selection for Embedded Real-time Control [Poster - Work In Progress Track]
Rajorshee Raha, Soumyajit Dey, Partha Pratim Chakrabarti, Pallab Dasgupta
51st Design Automation Conference (DAC), San Francisco, CA, 7-11 June 2014.


Handling Fault Detection Latencies in Automata-based Scheduling for Embedded Control Software.
Santhosh Prabhu M, Aritra Hazra, Pallab Dasgupta and P. P. Chakrabarti.
In Proc. of IEEE Multi-Conference on Systems and Control (MSC), August 2013.


Model Checking Controllers with Predicate Inputs.
Santhosh Prabhu M and Pallab Dasgupta.
In Proc. of IEEE VLSI Design Conference, 2013.


Reliability Annotations to Formal Specifications of Context-Sensitive Safety Properties in Embedded Systems.
Aritra Hazra, Priyankar Ghosh and Pallab Dasgupta.
Forum on Specification and Design Languages (FDL) 2012: 36-43, September 2012.


Taming the Component Timing: A CBD Methodology for Real-time Embedded Systems.
Manoj Dixit, S Ramesh and Pallab Dasgupta.
In the proceedings of DATE 2010, Dresden, Germany.

• Policy Based Security Analysis in Enterprise Networks -A Formal Approach.
  Padmalochan Bera, S K Ghosh and Pallab Dasgupta.
  IEEE Transactions on Network and Service Management, 7(4), Dec 2010, 231-243.


Integrated Security Analysis Framework for an Enterprise Network-A Formal Approach.
Padmalochan Bera, S K Ghosh and Pallab Dasgupta.
IET Information Security, 4(4), 2010, 283-300.


A WLAN security Management Framework based on Formal Spatio-Temporal RBAC Model.
Padmalochan Bera, S K Ghosh and Pallab Dasgupta.
Journal of Security and Communication Networks, Aug 2010.


Formal Analysis of Security Policy Implementations in Enterprise Networks.
Padmalochan Bera, Pallab Dasgupta, S. K. Ghosh.
International Journal of Computer Networks & Communications (IJCNC), Vol 2(2), pp 56-73, July 2009.

A Spatio-temporal Role-based Access Control Model for Wireless LAN Security Policy Management.
Padmalochan Bera, Pallab Dasgupta, S. K. Ghosh.
Proceedings of 4th International Conference on Information Systems, Technology band Management (ICISTM-10): 76-88, March 2010.


A Formal Method for Detecting Semantic Conflicts in Protocols between Services with Different Ontologies.
Priyankar Ghosh and Pallab Dasgupta.
In Proc. Of International Conference on Web & Semantic Technology (WeST), 2010.


A Query based formal security analysis framework for enterprise LAN.
Padmalochan Bera, Soumya Maity, S K Ghosh and Pallab Dasgupta.
In the Proceedings of 10th International Conference on Computer and Information Technology 2010 (CIT 2010),June 2010.


Fault Analysis of Security Policy Implementations in Enterprise Networks.
Padmalochan Bera, Pallab Dasgupta, S. K. Ghosh.
In International Conference on Networks & Communications (NetCoM), December 2009.


A Novel Methodology to Assist Client Side Testing of Interactive Web Applications.
Priyankar Ghosh, Srobona Mitra, Pallab Dasgupta.
In International Conference on Information Technology (ICIT), December 2009.


A Verification Framework for Analyzing Security Implementations in an Enterprise LAN.
Padmalochan Bera, Pallab Dasgupta, S. K. Ghosh.
In Proceedings of IEEE International Advance Computing Conference (IACC), 1008-1015, March 2009.


Formal Verification of Security Policy Implementations in Enterprise Networks.
Padmalochan Bera, Pallab Dasgupta, S. K. Ghosh.
In the 5th International Conference of Information System Security (ICISS), December 2009.

• Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures.
  Priyankar Ghosh, Amit Sharma, P. P. Chakrabarti, Pallab Dasgupta.
  J. Artif. Intell. Res. (JAIR) 44: 275-333 (2012).


Solving constraint optimization problems from CLP-style specifications using heuristic search techniques.
P.Dasgupta, P.P.Chakrabarti, Arnab Dey, S.Ghose and W.Bibel.
IEEE Transactions in Knowledge and Data Engineering, 14 (2), 2002, 353-368.


Searching Game Trees under a Partial Order.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Artificial Intelligence, 82 (1996) 237-257.


Agent Searching in Uniform b-ary Trees: Multiple Goals and Unequal Costs.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Information Processing Letters, 58 (1996) 311-318.


Multiobjective Heuristic Search of AND/OR Graphs.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Journal of Algorithms, 20 (1996) 282-311.


New results on Multiobjective State Space Search.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Sadhana, 21, 3 (1996), 263-290.


A correction to Agent Searching in a tree and the optimality of Iterative Deepening.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Artificial Intelligence, 77 (1995) 173-176.


Utility of Pathmax in Partial Order Heuristic Search.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Information Processing Letters, 55 (1995) 317-322.


Agent Searching in a tree and the optimality of Iterative Deepening.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Artificial Intelligence, 71 (1994) 195-208.

Ordered Solution Generation for Implicit AND/OR Search Spaces.
Priyankar Ghosh, P. P. Chakrabarti, Pallab Dasgupta.
In PReMI, 2013.


Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures.
Priyankar Ghosh, Amit Sharma, P. P. Chakrabarti, Pallab Dasgupta.
Extended Abstract in 23rd International Joint Conference on Artificial Intelligence (IJCAI), pp. 3156-3160, 2013.


Anytime Algorithms for Biobjective Heuristic Search.
Priyankar Ghosh, P. P. Chakrabarti and Pallab Dasgupta.
25th Australasian Joint Conference on Artificial Intelligence: 230-241, December 2012.


Execution Ordering in AND/OR Graphs with Failure Probabilities.
Priyankar Ghosh, P. P. Chakrabarti and Pallab Dasgupta.
In the 5th Annual Symposium on Combinatorial Search (SOCS), July 2012.


Instruction set extension exploration using Decomposable Heuristic Search.
S.Das, P.P. Chakrabarti, P.Dasgupta.
In Proc. of VLSI Design, 2006.


A Heuristic Search approach to effectively solve Constraint Optimization Problems from Logical Specifications.
P.Dasgupta, P.P.Chakrabarti, A.Dey, S.Ghose, and W.Bibel.
In Proc. of KBCS-98, 1998, 39-49.


A new competitive algorithm for Agent Searching in Unknown Streets.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Lecture Notes on Computer Science, Springer Verlag, Vol 1180, pp 147-155. Proceedings of the 16th FST & TCS conference (1996).


Game Tree Search under a Partial Order.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Proc. of 4th National Seminar on Theoretical Computer Science, Kanpur, India, pp 40-52, 1995.


Heuristic search using multiple objectives.
P.Dasgupta and P.P.Chakrabarti.
Proc. of 3rd National Seminar on Theoretical Computer Science, Kharagpur, India, pp 352-364, 1994.


Multiobjective Search in VLSI Design.
P.Dasgupta, P.Mitra, P.P.Chakrabarti and S.C.DeSarkar.
VLSI'94, Proc. of 7th IEEE Int. Conf. on VLSI Design, Calcutta, India, pp 395-400, 1994.

Online Prognosis for Priority Power Supply Restoration
Antara Ain and Pallab Dasgupta
Sustainable Energy, Grids and Networks, 1(2), 61-68, Elsevier, 2015

Route optimization for an electric vehicle with priority destinations
S. Raagapriya, Antara Ain, Pallab Dasgupta
International Conference on Smart Technologies For Smart Nations (SmartTechCon), August, 2017, pp: 1244-1249


Solar Irradiance Prediction from Historical Trends using Deep Neural Networks
Arghya Mukherjee, Antara Ain, Pallab Dasgupta
In Proc. of IEEE International Conference on Smart Energy Grid Engineering, Oshawa, Canada, August 2018.


Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUs.
Antara Ain, Akshay Mambakam, Pallab Dasgupta, Siddhartha Mukhopadhyay.
VLSI Design 2017: 245-250

h f₀ : A Hybrid Pitch Extraction Method for Multimodal Voice.
Pradeep Rengaswamy, M Gurunath Reddy, Krothapalli Sreenivasa Rao, and Pallab Dasgupta.
Circuits, Systems, and Signal Processing, 1-14, 2020.


SongFo: A Spectrum-Based Fundamental Frequency Estimation for Monophonic Songs.
Pradeep Rengaswamy, Krothapalli Sreenivasa Rao, and Pallab Dasgupta.
Circuits, Systems, and Signal Processing, 2020.


Robust f₀ extraction from monophonic signals using adaptive sub-band filtering.
Pradeep Rengaswamy, M Kiran Reddy, Krothapalli Sreenivasa Rao, and Pallab Dasgupta.
Speech Communication, Vol: 116, PP: 77-85, 2020.


An automated framework for exploitable fault identification in block ciphers.
Sayandeep Saha, Ujjawal Kumar, Debdeep Mukhopadhyay, Pallab Dasgupta.
Accepted in Journal of Cryptographic Engineering.


Automatic Characterization of Exploitable Faults: A Machine Learning Approach
Sayandeep Saha, Dirmanto Jap, Sikhar Patranabis, Debdeep Mukhopadhyay, Shivam Bhasin, and Pallab Dasgupta
IEEE Transactions on Information Forensics and Security, 14(4), 954-968, 2018.


ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers
Sayandeep Saha, Debdeep Mukhopadhyay, Pallab Dasgupta
IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018(2): 242-276 (2018).


A heuristic for the maximum processor requirement for scheduling layered task graphs with cloning.
D.Das, P.Dasgupta and P.P.Das.
Journal of Parallel and Distributed Computing, 49 (1998), 169-181.


Agreement under faulty interfaces.
P. Dasgupta.
Information Processing Letters, 65 (1997), 125-129.


V_Thr: An Adaptive Load Balancing Algorithm.
P.Dasgupta, A.K.Majumder and P.Bhattacharya.
Journal of Parallel and Distributed Computing, 42 (1997), 101-108.

• ALAFA: Automatic Leakage Assessment for Fault Attack Countermeasures.
  Sayandeep Saha, S. Nishok Kumar, Sikhar Patranabis, Debdeep Mukhopadhyay, Pallab Dasgupta.
  DAC 2019 (full paper): 136:1-136:6.


A new approach for minimal environment construction for modular property verification.
Saikat Dutta, Soumi Chattopadhyay, Ansuman Banerjee, Pallab Dasgupta.
Proc. of Asian Test Symposium, 2015


Adaptive Raga identification based on Normalized Note Histogram features.
R. Pradeep, Prasenjit Dhara, K. S. Rao, Pallab Dasgupta.
ICACCI, 1491-1496, 2015


Breaking Redundancy-Based Countermeasures with Random Faults and Power Side Channel
Sayandeep Saha, Dirmanto Jap, Jakub Breier, Shivam Bhasin, Debdeep Mukhopadhyay, and Pallab Dasgupta
In Proc. of IEEE Int. Workshop Fault Diagnosis and Tolerance in Cryptography (FDTC), Amsterdam, 2018.


An Automated Framework for Exploitable Fault Identification in Block Ciphers – A Data Mining Approach
Sayandeep Saha, Ujjawal Kumar, Debdeep Mukhopadhyay and Pallab Dasgupta
Accepted for Publication in PROOFS 2017: 6th International Workshop on Security Proofs for Embedded Systems.


A Robust Non-Parametric and Filtering Based Approach for Glottal Closure Instant Detection
Pradeep Rengaswamy, Gurunath Reddy M, K. Sreenivasa Rao, Pallab Dasgupta
INTERSPEECH 2016: 1795-1799, ISCA, San Francisco, California, 2016


Planning with Action Prioritization and new Benchmarks for Classical Planning.
Kamalesh Ghosh, Pallab Dasgupta and S. Ramesh.
25th Australasian Joint Conference on Artificial Intelligence: 779-790 December 2012.


Quantified UML Collaboration Diagrams.
P. Worah, Ansuman Banerjee, P.P. Chakrabarti, Pallab Dasgupta.
VLSI Design and Test Symposium, Bangalore, India,(2008).


Detecting faults at the time they occur.
A.Kumar,S.Das,P.Dasgupta,P.P.Chakrabarti.
In Proc. of VDAT 2006.


A comparative analysis of BDD-based and rule-based reachability problems for Cellular Automata.
Jatindra K. Deka, P.Dasgupta and P.P. Chakrabarti.
In Proc. of ICCCD 2000, 2000.


Adaptive algorithms for scheduling static task graphs in dynamic distributed systems.
Prashanti Das, D.Das, and P.Dasgupta.
Lecture Notes in Computer Science, Sringer Verlag, Vol 1745, pp 143-150. Proceedings of HiPC'99, (1999).


A new method for transparent fault tolerance of distributed programs on a network of workstations using alternative schedules.
Dibyendu Das, P.Dasgupta and P.P.Das.
Proc. of IEEE 3rd International Conf. on Algorithms and Architectures for Parallel Processing (ICA3PP),Melbourne, Australia, 1997.


A near optimal strategy for the extended cow-path problem in the presence of relative errors.
P.Dasgupta, P.P.Chakrabarti and S.C.DeSarkar.
Lecture Notes on Computer Science, Springer Verlag, Vol 1026, pp 22-36. Proceedings of the 15th FST & TCS conference (1995).