The group has made significant contributions in the theoretical foundations, language formalisms, and core formal methods technology. The most important contributions in this domain are:
The group's work on logics for expressing quantitative artifacts is path-breaking and separates this work from the classical body of logic dealing with Boolean propositions and predicates. We introduced logics like Min-Max Computation Tree Logic, Quantified Computation Tree Logic, Fuzzy Real Time Temporal Logic, which have been extensively studied by other researchers. Very recently we have shown for the first time that reliability annotations on temporal logics can be used to obtain provable guarantees on reliability of component based dynamical systems.
Temporal logic based specifications are widely used in formal verification; however in practice, the task of developing formal specifications is greatly facilitated by using auxiliary formalisms. The group's work on auxiliary state machines is widely adopted in industrial practice. More recently we have shown that auxiliary automata and auxiliary functions can significantly enhance the expressive power of analog extensions of assertion languages. Our work has been used as one of the primary references in the Accellera Verilog-AMS subcommittee working towards introducing AMS assertions in Verilog-AMS standards.
Model checking techniques for formal verification primarily aim to prove formal properties on state machine representations of the design under test. Scalability is a major concern here since the state machines of real world systems are huge and (typically) do not fit in memory. In a seminal collaboration with Intel researchers, the group developed a reasoning framework, where coverage gaps between system-level properties and proven properties of components can be evaluated, thereby targeting the verification effort on specific component level properties, as opposed to the whole system. This design intent coverage methodology, was integrated into Intel's formal verification tool flow, has been jointly published, and also articulated in the monograph, "A Roadmap for Formal Property Verification", published by Springer in 2006. Later the methodology was extended to parametric reasoning for early time budgeting in component based real time automotive control systems and patented for that domain with General Motors.
In a recent work sponsored by the prestigious Semiconductor Research Corporation (SRC), the group has introduced a path-breaking concept called formal features. As opposed to assertions which have a Boolean outcome, features are real valued. Our language formalism for features enables the use of un-interpreted variables (called local variables) for computing real valued artifacts over matches of an underlying Boolean assertion. We have shown that features can express a wide range of properties in the control domain and the analog circuit domain.
The group's work on design automation methodologies for verification of digital and analog integrated circuits is recognized worldwide. Our research has been funded by Intel for more than 10 years, by Synopsys for more than 15 years, by National Semiconductor Corp for more than 10 years, and by Semiconductor Research Corporation (SRC) for more than 7 years. Dr Dasgupta's research in this domain has been recognized by the prestigious Technomentor Award from the Indian Electronics and Semiconductor Association (IESA), and the IBM Faculty award. Dr Dasgupta is the Vice Chair of the India Chapter of the IEEE Council on Electronic Design Automation, and an Associate Editor of the IEEE Transactions on Design Automation of Electronic Circuits and Systems. The most significant contributions in this domain are highlighted below.
Assertions or formal properties are extensively used in the verification of digital integrated circuits. With the wide proliferation of analog components in system-on-chip designs, the requirement for assertions describing analog and mixed-signal (AMS) behaviors has become very significant. The group has developed the foundations of AMS assertions and their integration with industrial simulators and formal engines. We have done ground-breaking research on synchronizing AMS assertions with AMS simulation, trace debugging, and sampling refinement. Our AMS assertion tool developed under the SRC contract is the first industrially accepted tool in the domain and has been adopted by Freescale Semiconductors (a member of SRC). We have also contributed extensively in the past on methods for automatic generation of AMS behavioral models from hybrid automata skeletons in collaboration with National Semiconductor Corp, leading to the tool called CHASSIS. In another collaboration with POSOCO (the national power grid operators), our methods for AMS assertion monitoring are being re-engineered for monitoring phasor measurement data in electrical power grids.
Large scale circuits use complex power management strategies that dynamically regulate the operating voltage and clock frequencies of on-chip components. Bugs in the power management logic manifest themselves in form of data corruption (due to power droop and glitch related problems) and are among the hardest to debug. In collaboration with researchers from Synopsys we developed the first formal methodologies for verifying on-chip power management logic against formally specified architectural power management strategies. The PhD thesis of Aritra Hazra, won the prestigious ACM Best Dissertation Award (India) for this work. Currently Intel is collaborating with the group to expand the solution to mixed-signal power management logic.
Post-silicon bugs are often fixed by local patches deep inside the glue logic, but it is notoriously difficult to guarantee that the fix eliminates the bug and all its variants. The group was challenged by Intel to develop a methodology for analyzing the quality of the bug fix. We developed a taxonomy of bug fixes and a formal methodology for classifying bug fixes into this taxonomy, thereby enabling the designer to focus verification effort as required. We also developed the first of its kind methodology for learning assertions on the interface of the patched portion of the logic and using the assertions to rank potential counter-example scenarios in terms of their probability of being real. These methods reported outstanding correlation with real bug scenarios. Dr Srobona Mitra won the Google Women in Engineering Award in 2012 for this work. In collaborations with Synopsys, we have developed techniques for formal verification in a wide variety of domains, including industrial architectures and bus-functional models. Our work on the extraction of formal assumptions from constrained random test benches resulted in a joint US patent with Synopsys. In recognition of the expanding relationship with our institute, Synopsys awarded the Charles Babbage grant to IIT Kharagpur (first time in India) and set up the Synopsys CAD Lab at IIT Kharagpur (first of its kind).
In a recent work sponsored by the prestigious Semiconductor Research Corporation (SRC), the group has introduced a path-breaking concept called formal features. As opposed to assertions which have a Boolean outcome, features are real valued. Our language formalism for features enables the use of un-interpreted variables (called local variables) for computing real valued artifacts over matches of an underlying Boolean assertion. We have shown that features can express a wide range of properties in the control domain and the analog circuit domain.
We have made extremely significant contributions in several safety critical domains. Some of these contributions are extremely significant for the
nation:
We have been engaged by Indian Railways to examine the best practices in development of the yard-specific logic for electronic interlocking equipment being deployed for signaling and interlocking. Our prescription for formally validating the signaling logic as per the recommendation of the EN50128 railway safety standards was articulated by Dr Dasgupta jointly with Mr Mahesh Mangal of the Railway Board in a book chapter, Formal Assurance of Signaling Safety: A Railways Perspective in Handbook of Research on Emerging Innovations in Rail Transportation Engineering. We developed the notion of perfect invariants for proving signaling logic to be strongly safe. Based on this new technology, the group developed the first of its kind formal tool flow for formally proving the safety of signaling logic for Indian Railways. The tool has been successfully used in several stations in India. We have also helped IRISET (Signaling Institute of Indian Railways) in preparing a blueprint for a Center for Safety Critical Software.
In a very significant project called AUTOSAFE with the Technical University of Munich, Germany and two industry partners, we have jointly developed a platform for formal analysis of timing closure for control loop executions in software controlled automotive features. In a previous collaboration with General Motors, we introduced a theory that relates AI planning techniques with the verification of possible scenarios revealing contradictions between the formal specifications of multiple features. We shall lead the verification tasks in an Uchhatar Aviskar Yojana (UAY) project where Tata Motors and IIT Kharagpur have joined hands to develop their first plug-in hybrid electric vehicle.
We have developed formal methods for proving the security of access control configurations in enterprise networks. We have developed formal methods that can be used to prove the non-existence of hidden access paths that may be enabled by composition of multiple network services.
In a recent work sponsored by the prestigious Semiconductor Research Corporation (SRC), the group has introduced a path-breaking concept called formal features. As opposed to assertions which have a Boolean outcome, features are real valued. Our language formalism for features enables the use of un-interpreted variables (called local variables) for computing real valued artifacts over matches of an underlying Boolean assertion. We have shown that features can express a wide range of properties in the control domain and the analog circuit domain.