| ||||
| Sl. No. | Industry | Period | Specific Area and Point of Contact |
|---|---|---|---|
| 01 | Intel (Bangalore, India) | 2009 - 2012 | This group has an ongoing technology development
activity for formal post-silicon validation of bug-fixes in
Intel's processors. |
| 02 | Synopsys (Bangalore, India and Massachusetts, USA) |
2000 - 2008 | This group has developed several toolkits and
patented verification technologies for Synopsys, which
is the world leader in VLSI CAD tools. |
| 03 | National Semiconductor Corp., (Santa Clara, USA) |
2003 - 2007 | This group developed a tool for the Technology
Infrastructure Group of National Semiconductors
which is used for generating tests for custom cell
characterization. The tool uses formal methods
developed by the group. |
| 04 | Intel (Folsom, USA and Haifa, Israel) | 2002 - 2005 | Formal methods developed by nominee for verification
of architectural properties and computing formal
coverage metrics was integrated into Intel's Formal
Verification tool suite developed at Intel, Haifa. |
| Sl. No. | Industry | Period | Specific Area and Point of Contact |
|---|---|---|---|
| 01 | Semiconductor Research Corporation(SRC), USA | 2008 - 2016 | This group is currently developing technology for
verification of formal analog properties over AMS
simulators. SRC is a world famous research
consortium of companies like Intel, Texas Instruments,
IBM, and Freescale Semiconductors. |
| 02 | National Semiconductor Corp.,(Greenock, Scotland) | 2007 - 2010 | This group introduced methods for verifying
integrated power management units (PMUs) which
are large integrated AMS circuits used in portable
power devices like cell phones, PDAs and Laptops.
The methods use formal hybrid automata based
behavioral models. |
| Sl. No. | Industry | Period | Specific Area and Point of Contact |
|---|---|---|---|
| 01 | Intel (Bangalore, India) | 2010 - 2012 | Technology developed by the group has been used
in a tool for evaluating power management strategies
for mobile portable platforms. |
| 02 | Synopsys (California, USA and Bangalore, India) | 2008 - | This group is currently the Director of Synopsys
CAD Labs, IIT Kharagpur. He is also leading a project
in this Lab for developing formal verification
technology for verifying the architectural power
management strategy of large integrated circuits. A
tool has already been developed using the group's
technology. |
| Sl. No. | Industry | Period | Specific Area and Point of Contact |
|---|---|---|---|
| 01 | General Motors (India and Warren, USA) | 2009 - 2012 | This group has an ongoing activity for applying
novel formal methods in verifying feature
specifications for automotive control subsystems. |
| 02 | General Motors (India Science Labs) | 2007 - 2009 | Technology for verification of formal properties on the
fly over execution traces of UML state-charts was
integrated into a tool being used by GM for verification
of automotive control software. |
| Sl. No. | Industry | Period | Specific Area and Point of Contact |
|---|---|---|---|
| 01 | Google Inc. | 2008 - 2009 | This was a one-time research grant from Google for
developing formal methods for verifying web-service
protocols. |
| Sl. No. | Industry | Period | Specific Area and Point of Contact |
|---|---|---|---|
| 01 | Indian Railways | 2013 - | First phase of a project for using formal methods for
checking the correctness of Electronic Interlocking
Logic for railway signaling. |