Sumana Ghosh

Ph.D.
Department of Computer Science and Engineering
Indian Institute of Technology Kharagpur

Address : Formal Methods Lab, Room No. CSE-118, Ground Floor, CSE Building
Department of Computer Science and Engineering,
IIT Kharagpur, West Bengal 721 302, INDIA.
Email: sumanaghosh [at] cse [dot] iitkgp [dot] ernet [dot] in

Hi! I have recently completed my Ph.D. degree from the department of Computer Science and Engineering at IIT Kharagpur under the supervision of Prof. Pallab Dasgupta and Prof. Soumyajit Dey. You will find my curriculum vitae here [CV].

Design, Verification, and Analysis of Embedded Control Systems
Application of Formal Techniques in Real-Time Scheduling and Fault-tolerant Control Design
Automotive Security, Cyber-Physical Systems Security
Formal Methods and Robotics

2019: Doctor of Philosophy (Ph.D.) from Dept. of Computer Science and Engg., Indian Institute of Technology Kharagpur

Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta
Pattern Guided Integrated Scheduling and Routing in Multihop Control Networks
Accepted in ACM Transaction on Embedded Computing Systems (TECS) 2020.

Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta
Performance and Energy Aware Robust Specification of Control Execution Patterns under Dropped Samples
IET Computers & Digital Techniques(CDT), Volume: 13, Issue: 6, pp: 493–504(11), Nov, 2019, DOI: 10.1049/iet-cdt.2019.0030.

Sumana Ghosh, Soumyajit Dey and Pallab Dasgupta
Co-synthesis of Loop Execution Patterns for Multi-Hop Control Networks
IEEE Embedded System Letters, Volume: 10, Issue 4, pp 111-114, December 2018.

Sumana Ghosh, Souradeep Dutta, Soumyajit Dey and Pallab Dasgupta
A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control
ACM Transactions on Embedded Computing Systems, Volume: 16, No: 5s, Article: 189, pp 1-22, September 2017.

Sumana Ghosh, Soumyajit Dey, Pallab Dasgupta
Performance driven Post Processing of Control Loop Execution Schedules
ACM Transactions on Design Automation of Electronic Systems(in submission).

Sumana Ghosh, Soumyajit Dey and Pallab Dasgupta
Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples
32nd International Conference on Embedded and VLSI Design, pages 1-6, January 2019 (to appear).
Best Paper Award Nominee and won Honorable Mention Award

Sumana Ghosh, Souradeep Dutta, Soumyajit Dey, Pallab Dasgupta
A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control
International Conference on Embedded Software (EMSOFT), journal version appeared in ACM TECS, Seoul, South Korea, September 2017.

Sumana Ghosh and Pallab Dasgupta
Formal Method for Pattern Based Reliability Analysis in Embedded System
28th International Conference on Embedded and VLSI Design, pp 192-197, January 2015.

Presented “Synthesizing Performance-aware (m,k)-firm Control Execution Patterns under Dropped Samples”, at the IEEE VLSID Conference, January 2019, held at New Delhi, India.
Worked as Research Consultant in the project FMSAFE: A Networked Centre for Formal Methods in Validation and Certification Procedures for Safety Critical ICT Systems, sponsored by MHRD and Ministry of Railways, for a period of: January 2018 to January 2019.
Presented "A Structured Methodology for Pattern based Adaptive Scheduling in Embedded Control", at the ACM SIGBED International Conference on Embedded Software (EMSOFT), October 2017, held at Seoul, South Korea.
Delivered talk on “Formal Methods for Verification of Real-Time Embedded Control ”, at the Indo-Israel Workshop, February 2016, held at IIT Kharagpur.
Worked as Research Consultant in the project AUTOSAFE: Architecture-aware Timing Analysis and Optimization of Safety-Critical Automotive Software, sponsored by Indo-German Science and Technology Center (IGSTC), for a period of: July 2014 to December 2015.
Delivered talk on “An Algorithmic Bridge from Adaptive Sampling to Automata- based Scheduling for Embedded Control”, at the Indo-German Workshop, December 2015, held at IIT Kharagpur.
Presented "Formal Methods for Pattern Based Reliability Analysis in Embedded Systems", at the IEEE VLSID Conference, January 2015, held at Bangalore, India.

Received Honorable Mention Award in VLSID Conference 2019
Awarded Research Fellowship by Ministry of Human Resource Development (MHRD) for a tenure of 5 years (2013-2018).
Qualified UGC NET (University Grants Commission - National Eligibility Test) with Junior Research Fellowship award in Computer Science and Application, December 2012.
The prestigious Mamraj Agarwal National Award and University Gold Medal for standing First in M.Sc Exam, 2012.
M.Sc (Computer and Information Science), 1st Class First (Rank-1), University of Calcutta, 2012.
Qualified GATE (Graduate Aptitude Test in Engineering) in Computer Science in 2012 with a percentile of 99.27.

Formal Languages and Automata Theory (CS21004; Spring 2018, 2017, 2014)
Computational Foundation of Cyber-physical Systems (CS61063; Autumn 2017)
Programming & Data Structures Lab (CS19001; Autumn 2016, 2015, Spring 2013)
Database Management Systems (CS43002; Spring 2016, 2015)
Advanced Graph Theory (CS60047; Autumn 2014)
Foundations of Computing Science (CS60001; Autumn 2013)
Introduction to Algorithm Design course in a programme named "Train 10,000 Teachers (T10kT)", under the project ’Empowerment of Students/Teachers’, sponsored by National Mission on Education through ICT (MHRD, Government of India), 2015.

Guest Lecturer at Asutosh College, Affiliated to University of Calcutta
Working period : June 2012 to November 2012.