Our present expertise apart from the conventional understanding of cryptographic algorithms and protocols, have been in the implementation of cryptographic algorithms on FPGAs. We have developed several designs of AES, ECC, which are the world wide standard algorithms used for bulk encryption, and authentication. The designs have been deployed in several organizations like Center for Artificial Intelligence and Robotics (CAIR), DRDO-labs and used for real life purposes. To make a special note, the laboratory has recently developed the fastest ECC core for FPGAs, which also takes the smallest area on FPGAs among reported state-of-the-art (published in CHES 2012). We have also infrastructure for performing power attacks, with high end equipments and in-house developed softwares for performing statistical analysis of the acquired power traces. The laboratory also has a test bed for performing fault attacks through clock glitches on several ciphers including the full round AES. The team has the record of developing the strongest fault attack on AES, showing that a single well-formed fault can reduce the AES key to only 256 values. The team has also produced several cache attacks on actual implementations of ciphers, running on standard Intel Core-2 Duo processors, and have published strong results in top crypto conferences like CHES, Indocrypt, CT-RSA etc. We have also been working along with in the design of countermeasures against the side channels, providing suitable defences against power attacks, incorporating fault tolerance, and defending against cache attacks. However the central goal in all these countermeasures has been to develop defences by design, so as to reduce the overhead of countermeasures and also to provide better guarantees for security: a combination which is extremely challenging to attain. The group also been working in designing indigenous light weight ciphers: a prototype of which has been handed over to ISRO, India.