Prof. Debdeep Mukhopadhyay

  • Architecture specific high-speed block cipher implementation : Filed (Ref : RFI-110125 )
  • A cache Timing Attack resistant Prefetching Architecture : Submitted (Ref : )

Prof. R.S. Chakraborty

  • Protection of Intellectual Property (IP) Cores Through a Design Flow: Granted (Ref : US Patent No. 8402401 )
  • Multi-Level Inline Data Deduplication: Submitted (Ref : International PCT Application No. PCT/IB2012/055688; Indian Patent Application No. 1022/KOL/2012 )
  • A Method and System for Evaluation of Reversible Watermarking of Digital Images and Audio : Filed (Ref : 853/KOL/2013 )
  • Architecture and Design Automation of High Performance Large Adders and Counters on FPGA through Constrained Placement : Filed (Ref : International PCT Application Ref: PCT/IB2014/060372. Indian Patent Ref.: 179/KOL/2014 )
  • System and Method for Dynamic Partial Reconfiguration of Circuits Mapped or Configured on FPGA Platform : Filed (Ref : 806/KOL/2015 )