B.Tech, M.Tech, and Ph.D from the Indian Institute of Technology Kharagpur.

My current research focus is on automated formal and semi-formal techniques for verification, mainly targetted towards design verification in VLSI CAD. We work with several companies on related areas.

My other interests include combinatorial optimization, logic, deduction and distributed algorithms.

Current CV download from here

	Position:
	Position held Institution From To ACADEMIC POSITIONS   Visiting Lecturer (Tenure track) IIT Kharagpur Dec 1995 Feb 1998   Assistant Professor, Computer Sc & Engg IIT Kharagpur Mar 1998 Jun 2002   Associate Professor, Computer Sc & Engg I.I.T. Kharagpur Jul 2002 Mar 2007   Professor, Computer Sc & Engg I.I.T. Kharagpur Apr 2007 Aug 2013   HAG Professor, Computer Sc & Engg I.I.T. Kharagpur Aug 2013 - INSTITUTE LEVEL ADMINISTRATIVE POSITIONS   Professor-In-Charge, Advanced VLSI Design Lab IIT Kharagpur Oct 2007 Sep 2010   Associate Dean (Sponsored Research & Industrial Consultancy) IIT Kharagpur Oct 2013 Jul 2016   Dean (Sponsored Research & Industrial Consultancy) I.I.T. Kharagpur Aug 2016 - LEADERSHIP POSITIONS   Director, Synopsys CAD Laboratory (Funded by Synopsys, this center of excellence executes multiple projects in diverse areas of VLSI CAD) IIT Kharagpur Nov 2009 -   Co-Principal Investigator, Center for Artificial Intelligence for Societal Needs IIT Kharagpur Dec 2013 -   Chairman, Advanced VLSI Consortium (consortium of 15 semiconductor and EDA companies) I.I.T. Kharagpur Oct 2007 Sep 2010
	Awards / Professional Recognition:
	FELLOWSHIPS OF NATIONAL ACADEMIES AND PROFESSIONAL BODIES Fellow of the Indian Academy of Science (2015) Fellow of the Indian National Academy of Engineering (2012) Fellow of the Institution of Electronics and Telecom Engineers, India (2013) FELLOWSHIPS OF NATIONAL ACADEMIES AND PROFESSIONAL BODIES TECHNOMENTOR AWARD (2012) from the Indian Electronics and Semiconductor Association -- for outstanding contributions in the field of Semiconductors / Electronics IBM Faculty Award (2007) -- globally competitive awards given annually by IBM Fellow of the Institution of Electronics and Telecom Engineers, India (2013) AWARDS FROM NATIONAL ACADEMIES Young Scientist Medal of Indian National Science Academy (1999) Young Engineer Medal of Indian National Academy of Engineering (2002) Associate Fellow of the Indian Academy of Sciences (1998 – 2002) AWARDS RECEIVED AS A STUDENT Institute Silver Medal for 1st rank in BTech, Computer Sc & Engineering, IIT Kharagpur (1990) (Also ranked second among all branches) Institute Silver Medal for 1st rank in MTech, Computer Sc & Engineering, IIT Kharagpur (1992) Jagadis Bose National Science Talent Search Scholarship (1986 – 1990) OTHER FORMS OF RECOGNITION Listed as one of top 10 contributors in Computer Science in India in terms of number of publications during 2002 to 2014 as per the bibliometric study: International Comparative Performance of India’s Research Base (2009-14) – A bibliometric analysis.  The study was commissioned by the Dept. of Science and Technology, Govt. of India. (Available online at: http://nstmis-dst.org/PDF/Elsevier.pdf and at https://www.elsevier.com/research-intelligence/research-initiatives/india-research-performance ) Associate Editor, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems Vice Chair of IEEE Council on Electronic Design Automation (CEDA), India Chapter Former member of Council of Indian Association for Research in Computer Science (IARCS)
	Patents:
	US PATENT No: US 7,797,123 Sep 14, 2010 Method and Apparatus for Extracting Assume Properties from a Constrained Random Test Bench, Inventors: K.Dey, E.Cerny, Pallab Dasgupta, B.Pal, P.P.Chakrabarti. This patent describes a technique for automatically extracting formal logical constraints on the environment of a circuit, where the environment is described by means of a test-bench developed in SystemVerilog. Developing environment constraints (called assume properties) is a non-trivial task and is one of the main concerns in formal verification of reactive systems. The patented technique automated this problem. The patent was jointly obtained with collaborators from Synopsys Inc, and is assigned to Synopsys. US PATENT No: US 8,082,140, Dec 20, 2011 Parametric Analysis of Real Time Response Guarantees on Interacting Software Components, Inventors: M.Dixit, S.Ramesh, Pallab Dasgupta. This patent describes a technique for automatic extraction of linear constraints on the timing of constraint behaviors that are obtained by formally comparing the conjunction of component specifications with formal time-critical end-to-end behaviors in automotive features. The patented technique enables early timing analysis with the help of formal specifications in the development of automotive control features and sub-system technical specifications. The patent was jointly obtained with collaborators from General Motors, and is assigned to General Motors.