Devleena Ghosh Research Scholar (PhD Student) Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Address : Formal Methods Research Lab, Room No. 118, Ground Floor, CSE Building                   Department of Computer Science and Engineering,                   IIT Kharagpur, West Bengal 721 302, INDIA. Email:       devleena.ghosh [at] iitkgp [dot] ac [dot] in ; devleena.ghosh07 [at] gmail [dot] com

About

Research Interests

• Computational Biology
• Formal Methods

Education

• 2013:   M.Tech. in Computer Science and Engineering (Summa Cum Laude) from Indian Institute of Technology, Kharagpur .
  Masters Thesis : Formal Modeling and Verification of Interlocking for Railway Signaling Systems
  Advisor : Prof. Chittaranjan Mandal


• 2010:   B.E. in Computer Science and Technology from IIEST, Shibpur (formerly Bengal Engineering and Science University, Shibpur)
  Bachelor Thesis : Iris Recognition
  Advisor : Prof. Sekhar Mandal


• 2006:   Higher Secondary (Class XII Board Exam)
Board:   West Bengal Council Higher Secondary Education


• 2004:   Madhyamik (Class X Board Exam)
Board:   West Bengal Board of Secondary Education

Publications      

Journals

1. COLDVL: a virtual laboratory tool with novel features to support learning in logic design and computer organisation
   Gargi Roy, Devleena Ghosh, Chittaranjan Mandal
   Journal of Computers in Education (2017), pp 1-30
   doi: 10.1007/s40692-017-0091-8

Conferences

1. Layout Validation using Graph Grammar and Generation of Yard Specific Safety Properties for Railway Interlocking Verification
   Devleena Ghosh, Chittaranjan Mandal
   22^nd Asia Pacific Software Engineering Conference (APSEC) 2015, New Delhi, December, 2015.


2. A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization
   Gargi Roy, Devleena Ghosh, Chittaranjan Mandal
   7^th IEEE International Conference on Technology for Education (T4E) at NIT Warangal, India, December, 2015.


3. Aiding Teaching of Logic Design and Computer Organization Through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool
   Gargi Roy, Devleena Ghosh, Chittaranjan Mandal, Indraneel Mitra
   7^th IEEE International Conference on Technology for Education (T4E) at NIT Warangal, India, December, 2015.


4. A Virtual Laboratory for Computer Organisation and Logic Design (COLDVL) and Its Utilisation for MOOCs
   Gargi Roy, Devleena Ghosh, Chittaranjan Mandal
   3^rd International Conference on MOOC, Innovation and Technology in Education (MITE) 2015, Amritsar, October, 2015,

Communicated Papers

1. Clustering Based Parameter Estimation of Thyroid Hormone Pathway
   Devleena Ghosh, Chittaranjan Mandal

Work Experience

• Microsoft IDC, Hyderabad
Designation:   Software Engineer
Area : Visual Studio Online Services (Cloud Load Testing team)
Duration:   Aug 2013 - Dec 2015


• Department of CSE, IIT Kharagpur
  Designation:   Junior Research Fellow
  Project : Virtual Lab for Computer Organization and Architecture, sponsored by MHRD
  Duration:   Sept 2010 - Jun 2011
  

Activities

• Programming & Data Structures
• Foundations of Computing Science
• Formal Systems
• Algorithms