Journal Publications

1. Web-based Course management and Web Services, Electronic Journal of e-Learning, pp 135-144, vol. 2, No. 1, 2004; C Mandal, Vijaya Luxmi Sinha, Chris Reade. ( Abstract / pdf paper )
2. Genetic Algorithms for High-Level Synthesis in VLSI Design, Materials and Manufacturing Processes, pp 355-383, vol. 18, No. 3, 2003; C. Mandal, P. P. Chakrabarti. (Text abstract / pdf paper).
3. GABIND: A Genetic Algorithm Approach to Allocation and Binding for the High-Level Synthesis of Data Paths, IEEE Transactions on VLSI, pp 747-750, vol. 8, No. 6, December 2000; C. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
4. A Design Space Exploration Scheme for Data Path Synthesis, IEEE Transactions on VLSI, pp 331-338, vol. 7, No. 3, 1999; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
5. A Probabilistic Estimator for the Vertex Deletion Problem, Computers and Mathematics with Applications, pp 1-4, vol 35, No. 6, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
6. Complexity of Fragmentable Object Bin Packing and an Application, Computers and Mathematics with Applications, pp. 91-97, vol. 35, No.11, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
7. Some New Results in the Complexity of Allocation and Binding in Data Path Synthesis, Computers and Mathematics with Applications, pp 93-105, vol 35, No. 10, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper).
8. Complexity of Scheduling in High Level Synthesis, VLSI DESIGN, pp 337-346, vol. 7, No. 4, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper)
9. Register-Interconnect Optimization in Data Path Synthesis, Microprocessing and Microprogramming, pp. 279-288, vol. 33, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
10. Allocation of registers to multiport memories based on register-interconnect optimization, Modelling and Simulation, pp. 57-64, vol. 25, no. 4, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.

Conference/Seminar Proceedings

1. A Web-based Automatic Evaluation System, 3nd European Conference on e-Learning, Paris, France, pp -, 2004, C. Mandal, V. L. Sinha, C. M. P. Reade. (Text abstract / Extended abstract / pdf paper / rtf paper )
2. A New Approach to Timing Analysis using Event Propagation and Temporal Logic, Proceedings of DATE '04, Paris, France, pp 1198 - 1203, 2004, Arijit Mondal, Partha P Chakrabarti, C. Mandal. (Text abstract / pdf paper )
3. A Web-Based Course Management Tool, 2nd European Conference on e-Learning, Glasgow, UK, pp 293-302, 2003, C. Mandal, V. L. Sinha, C. M. P. Reade. (Text abstract / pdf paper )
4. Timing Analysis of Tree-like RLC Circuits, IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, USA, pp. 838-841, 2002, Rajendran, B., Kheterpal, V., Das, A., Majumder, J., Mandal, C., Chakrabarti, P.P. (Text abstract / pdf paper )
5. A Genetic Algorithm for the Synthesis of Structured Data Paths, Proceedings of IEEE VLSI Design 2000, Calcutta, INDIA, pp. 206-211, 2000; C. Mandal, R. M. Zimmer. (Text abstract / postscript paper )
6. Integrated Scheduling and Allocation for Synthesis of Structured Data Paths, IEEE VLSI Design & Test Workshops, August 6-7, 1998,, The Habitat World, Lodi Road, New Delhi, India, on-line proceedings; C. Mandal, R. Zimmer. (Text abstract)
7. High-Level Synthesis of Structured Data Paths, IFIP TC10 WG 10.5 International Conference on Computer Hardware Description Languages and Their Applications, 20-25 April 1997, Toledo, Spain; pp. 92-94; C. A. Mandal, R. M. Zimmer. (Extended version available) (Text abstract / postscript paper)
8. Design Space Exploration for Data Path Synthesis, Proceedings of IEEE VLSI Design '97, Hydrabad, INDIA, pp. 166-173, 1997; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper (extended version))
9. Allocation and Binding for Data Path Synthesis Using a Genetic Approach, Proceedings of IEEE VLSI Design '96, Bangalore, INDIA, pp. 122-125, 1996; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper (extended version) )
10. Port Assignment for Dual and Triple Port Memories Using a Genetic Approach, Proceedings of IFIP Asia/Pacific Conference on Hardware Description Languages Bangalore, INDIA, pp. 60-64, 1996; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Text abstract / postscript paper)
11. Use of Multi-Port Memories in Programmable Structures for Architectural Synthesis Proceedings of ISIS Austin, pp. 341-351, 1996; C. A. Mandal, R. M. Zimmer.
12. Allocation of Registers to Multi-port Memories Based on Register--Interconnect Optimization, Proceedings of ICAUTO -International Conference- 1995, Indore , pp. 611-614, 1995; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
13. A Framework for High Level Synthesis, International Workshop on Artificial Intelligence, I.I.M., Calcutta, March, 1994; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
14. Complexity of Scheduling 2-Operation Chains and Some Other Related Scheduling Problems, Proceedings of the Fourth National Seminar on Theoretical Computer Science, IIT Kanpur, INDIA, pp. 171-180, 1994; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
15. Interconnect Optimization Techniques in Data Path Synthesis, Proceedings of IEEE VLSI Design '92, Bangalore, pp. 85-90, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
16. ABS: An Automated Behavioural Synthesis System, Proceedings of VLSI Design '90, Bangalore, pp. 18-23, 1991; C. A. Mandal, P. Pal Chaudhuri.

PhD Thesis