CS60089 : Testing and Verification of Circuits Autumn 2018   L-T-P: 3-1-0
!! SORRY, THIS COURSE HAS BEEN DISCONTINUED IN THIS SEMESTER !!
Information |  Notices |  Announcements |  Syllabus |  References

General Information

Instuctor     Dr. Aritra Hazra
Timing     Slot F4   [ Wednesday (10:00–10:55),  Thursday (09:00–09.55),  Friday (11:00–12:55) ]
Venue     Room No. CSE-120 (Ground Floor, CSE Department)
Teaching Assistants     Sudipa Mandal   and   Sayandeep Saha

Notices

  • Prerequisites: This course has no official prerequisites. However, it is desirable that students registering for this course have completed the basic courses on – (i) digital logic/circuits and (ii) programming and data-structures in their undergraduate/graduate level.

  • Selection Procedure: Interested students are requested to apply via the ERP portal. The timings for this course as mentioned above is to be treated as frozen and final. An applicant must not have any clash with these timings. If so, the students are supposed to make attempts to shift the other courses/labs clashing with this.

    • Announcements

    July 20, 2018

    Due to clash in slots (conflicting requirements from the willing students from CSE, ECE and EE branches) and hence lack of participation in CS60089 (Testing and Verification of Circuits) course, I am sorry to inform you that this course is discontinued. I sincerely apologize for the inconvenience created.

    July 15, 2018

    Classes will commence from 18-Jul-2018 (Wednesday).

    Course Outline

    Topic Content Tentative-Schedule Slides
    Introduction to Verification and Testing Overview of design verification and testing. 2-hours  Lecture-1  |  Lecture-2 
    Verilog HDL Writing designs and test-benches using Verilog. 4-hours
    Simulation Framework Event-driven and Cycle-based simulators. 3-hours
    Simulation Coverage Test scenarios and Test plan, Coverage notions and metrics. 3-hours
    Design Specification Temporal Logics (LTL + CTL), SystemVerilog Assertions. 5-hours
    Design Representation Binary decision diagram, Formal modeling of state machines and Equivalence checking. 6-hours
    Model Checking LTL and CTL model checking, Bounded model checking. 4-hours
    NuSMV Usage NuSMV Basics, Model checking using NuSMV. 3-hours
    Abstraction and Refinement Counter-example guided abstraction refinement framework. 3-hours
    Formal Verification Coverage Consistency (Realizability and Receptiveness), Coverage notions and metrics. 3-hours
    Introduction to Testing Overview of circuit testing. 1-hour
    Test Modeling and Simulation Fault modeling, Logic simulation and fault simulation. 4-hours
    Testability Analysis SCOAP measures, Controllability and Observability. 2-hours
    Automatic Test Pattern Generation Combinational ATPG, Sequential ATPG. 3-hours
    Design for Testability Scan chains and Scan structure design. 2-hours
    Built-in-Self-Test BIST structure, Logic BIST architecture. 4-hours
    Memory Testing MATS+ March tests, NPSF tests. 2-hours

    Books and References

    [1]     William K Lam; Hardware Design Verification: Simulation and Formal Method-Based Approaches; Prentice Hall Modern Semiconductor Design Series, 2005.
    [2]     Pallab Dasgupta; A Roadmap for Formal Property Verification; Springer, 2006.
    [3]     Michael Huth and Mark Ryan; Logic in Computer Science: Modelling and Reasoning about Systems; Cambridge University Press, 2004.
    [4]     Edmund M. Clarke, Orna Grumberg and Doron A. Peled ; Model Checking; The MIT Press, 1999.
    [5]     Christel Baier and Joost-Pieter Katoen; Principles of Model Checking; The MIT Press, 2008.
    [6]     Michael L. Bushnell and Vishwani D. Agrawal; Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits; Kluwer Academic Publishers, 2002.
    [7]     Niraj K. Jha and Sandeep Gupta; Testing of Digital Systems; Cambridge University Press, 2004.
    [8]     Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman; Digital Systems Testing and Testable Design; Wiley-IEEE Press, 1993.
    [9]     Laung-Terng Wang, Cheng-Wen Wu and Xiaoqing Wen; VLSI Test Principles and Architectures; Morgan Kaufman Publishers, 2006.
    [10]     Paul H. Bardell, William H. McAnney and Jacob Savir; Built-in Test for VLSI: Pseudorandom Techniques; Wiley Interscience, 1987.
    [11]     Parag K. Lala; Fault Tolerant and Fault Testable Hardware Design; Prentice-Hall International, 1985.

    Information |  Notices |  Announcements |  Syllabus |  References