Prof. Pallab Dasgupta

  Professor, Department of Computer Science and Engineering
  DEAN, Sponsored Research and Industrial Consultancy
  Indian Institute of Technology Kharagpur
  Email: pallab[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Prof. Partha Pratim Chakrabarti

  Director, Indian Institute of Technology Kharagpur
  Professor, Department of Computer Science and Engineering
  Email: ppchak[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Dr. Soumyajit Dey

  Assistant Professor, Department of Computer Science and Engineering
  Indian Institute of Technology Kharagpur
  Email: soumya[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Antara Ain

  PhD, Advanced Technology Development Centre.
  Formal Methods Laboratory, Dept of CSE
  Indian Institute of Technology Kharagpur
  Email:

  Sumana Ghosh

  PhD, Department of Computer Science and Engineering
  Formal Methods Laboratory
  Indian Institute of Technology Kharagpur
  Email: sumanaghosh[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Rajorshee Raha

  PhD, Department of Computer Science and Engineering
  Formal Methods Laboratory
  Indian Institute of Technology Kharagpur
  Email: rajorshee[DOT]raha[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Antonio A. Bruto Da Costa

  PhD, Department of Computer Science and Engineering
  Formal Methods Laboratory
  Indian Institute of Technology Kharagpur
  Email: bruto[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Rajib Lochan Jana

  PhD, Department of Computer Science and Engineering
  Formal Methods Laboratory
  Indian Institute of Technology Kharagpur
  Email:

  Sudipa Mandal

  PhD, Department of Computer Science and Engineering
  Formal Methods Laboratory
  Indian Institute of Technology Kharagpur
  Email: sudipa[DOT]mandal[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Thakkar Jay A.

  PhD, Advanced Technology Development Centre.
  Formal Methods Laboratory, Dept of CSE
  Indian Institute of Technology Kharagpur
  Email: jay1992[AT]atdc[DOT]iitkgp[DOT]ernet[DOT]in

  I'm interested in Design and Verification methodologies for Embedded Control Software
  of Automotive/Avionic Systems.

  Sayandeep Saha

  PhD, Department of Computer Science and Engineering
  Formal Methods Laboratory
  Indian Institute of Technology Kharagpur
  Email: sahasayandeep[AT]cse[DOT]iitkgp[DOT]ernet[DOT]in

  Sayandeep Sanyal

  Dr. Kamalesh Ghosh

  Currently working in Synopsys
  Automated Planning Based Methods for Early Verification of Reactive Control Systems
 

  Dr. Aritra Hazra

  Currently holding faculty position at IIT Madras
  Formal Methods for Architectural Power Intent Verification and Functional Reliability
  Analysis

  Dr. Padmalochan Bera

  Currently holding Faculty Position at IIT Bhubaneswar
  Formal Analysis of Security Policy Implementations in Enterprise Networks

  Dr. Priyankar Ghosh

  Currently develops formal verification technology at IBM India, Bangalore
  Search Techniques for finding Alternative Solutions for AND/OR Graphs and Bi-objective
  Optimization Problems

  Dr. Srobona Mitra

  Currently Formal Verification Engineer at Synopsys India, Bangalore
  Formal Methods for Aiding Verification of Local Design Changes in Digital Integrated
  Circuits

  Dr. Rajkumar P.V.

  Currently Post Doc fellow at the Institute for Cyber Security, Univ of Texas, San Antonio,
  USA
  Formal and Semi-Formal Methods for Application Specific Usage Control and Security

  Dr. Subhankar Mukherjee

  Currently with Mentor Graphics, Bangalore
  Assertions - from a mixed-signal perspective

  Dr. Manoj Dixit

  Currently with Mathworks, Bangalore - formerly at GM India Science Labs
  Formal Methods for Early Time-Budgeting in Component-based Embedded Control
  Systems

  Dr. Arijit Mondal

  Currently holding Faculty Position at IIT Patna
  A symbolic event propagation approach for solving timing problems of digital circuits

  Dr. Bhaskar Pal

  Currentlyworking for Synopsys in Formal Verification
  Formal and semi-formal verification methods with constrained random test benches

  Dr. Suchismita Roy

  Currently holding Faculty Position at NIT Durgapur
  SAT Based Solutions for Timing and Power Estimation in Gate Level Circuits

  Dr. Ansuman Banerjee

  Currently holding Faculty Position at ISI Kolkta
  Formal Methods for accelerating formal, semi-formal and dynamic property verification
  through novel specification styles

  Dr. Sayantan Das

  Currently working for Verific/Electra Design Automation Pvt Ltd
  Formal Analysis of Property Specifications: Consistency, Coverage and Synthesis

  Dr. Prasenjit Basu

  Currently working for Samsung Research, Bangalore
  Design Intent Verification by Formal Property Coverage

  Dr. Jatin K. Deka

  Currently holding Faculty Position at IIT Guwahati
  Model checking techniques for Reasoning about Events and Extremal Properties in
  Timed Systems

  Shiladitya Ghosh