Tentative Schedule of Theory and Lab Classes

DATE

Topics

Monday 25-06-2012

Inauguration

Overview of FPGA & Xilinx, Spartan-3, FPGA based ckt. Boards, Reconfigurable Computing, Software Support for FPGA design, ISE, Testbench, RTL Simulator, Adding a Constraint file & Synthesize &
Implement the Code, ModelSim.

Lab: Gate-level ckts. i.e. HA & FA, MUX etc.

Tuesday 26-06-2012

Theory : Verilog modeling of Combinational Ckt.,
Simulation using Modelsim.

Lab: Sign Magnitude Adder, Gate level Binary
Decoder, Multifunctional Barrel Shifter.

Wednesday 27-06-2012

 

Theory : Verilog modeling of Regular Sequential Ckt

Lab: ShiftRegister,BinaryCounter, Programmable Square wave generator.

Thursday 28-06-2012

 

Theory : FSM & FSMD

Lab: Division Ckt., Binary-to-BCD conversion,
Period Counter, Fibonacci Number Ckt.

Friday : 29-06-2012

Theory : FSMD & I/O Modules

Lab: Alternative Coding Style for BCD Counter ,
FIFO Buffer, Fibonacci Ckt. & Testbench for FIFO Buffer.

Saturday : 30-06-2012

Quiz

Valedictory