Sudakshina Dutta Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Address : Formal Methods Research Lab, Room No. 118, Ground Floor, CSE Building                   Department of Computer Science and Engineering,                   IIT Kharagpur, West Bengal 721 302, INDIA. Email:       sudakshina [at] iitkgp [dot] ac [dot] in

About

Research Interests

• Formal Verification
• Program Analysis
• Abstract Interpretation
• Cognitive Science
• Artificial Intelligence

Education

• 2018:   PhD from Indian Institute of Technology Kharagpur
  Thesis : Validation of Optimizing and Parallelizing Transformations using Dependence Graph Abstraction
  Advisor : Prof. Dipankar Sarkar and Prof. Soumyajit Dey


• 2011:   M.Tech. in Computer Science and Engineering from Indian Institute of Technology Kharagpur .
  Masters Thesis : A Cognitive Approach to Word Sense Disambiguation
  Advisor : Prof. Anupam Basu


• 2007:   B.E. in Information Technology from Jadavpur University
  Bachelor Thesis : Mobile Cluster Management in a Distributed Information Network
  Advisor : Prof. Parama Bhaumik


• 2003:   Higher Secondary (Class XII Board Exam)
Board:   West Bengal Council Higher Secondary Education


• 2001:   Madhyamik (Class X Board Exam)
Board:   West Bengal Board of Secondary Education

Publications      

Conferences

1. Validation of Loop Parallelization and Loop Vectorization Transformations
   Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh
   11^th International Conference on Evaluation of Novel Approaches to Software Engineering (ENASE) 2016, Rome, Italy, April, 2016.


2. An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences
   Sudakshina Dutta, Dipankar Sarkar
   11^thInternational Conference on Evaluation of Novel Approaches to Software Engineering (ENASE) 2016, Rome, Italy, April, 2016.


3. A Cognitive Approach to Word Sense Disambiguation.
   Sudakshina Dutta, Anupam Basu
   13^th International Conference, CICLing 2012, New Delhi, India, March, 2012.

Journals

1. Synchronization Validation for Cross-Thread Dependences in Parallel Programs.
   Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat
   International Journal of Parallel Programming (IJPP), accepted(2016).


2. Validation of parallelizing transformations of sequential programs.
   Sudakshina Dutta
   Concurrency and Computation: Practice and Experience (CPE), vol. 29, no. 8, 2017.

Poster

1. Validation of Loop Concurrentization Transformations for Sequential Programs.
   Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat
   IMPECS-POPL Workshop on Emerging Research and Development Trends in Programming Languages (WEPL), Mumbai, India, 2015.

Work Experience

• Interra Systems
Designation:   Member of Technical Staff
Area : Developer of hierarchical integrated circuit mask layout data reader and writer libraries
Duration:   July 2007 - July 2009

Activities

• Intelligent Systems
• Programming and Data Structures
• Theory of Computation
• Compilers
• Computer Organization and Architectures
• Foundations of Computer Science
• Formal Systems
• Logics for Computer Science
• Computer Organization and Architecture

Code repository

Last updated: August, 2018.