This research focuses on efficient high speed implementations of elliptic curves on FPGA platforms. Although FPGAs offer more programmability and have lower costs compared to ASICs, designing with FPGAs is tricky. This research mainly focuses on efficient FPGA implementations of the arithmetic operations required for elliptic curves. Two of the most important primitives namely multiplication and inversion are studied. The work aims at demonstrating that efficient arithmetic operations is vital to obtain an efficient elliptic curve processor.


  • Verilog code for a high performance elliptic curve crypto processor over GF(2233) can be downloaded from here. The processor uses a hybrid Karatsuba algorithm for field multiplication and a quad Itoh Tsujii algorithm for field inversion. The scalar multiplier is implemented using a simple double and add algorithm. [ Download].

  • A tool to generate HDL code for Karatsuba multipliers of any size. Three multiplication techniques are supported namely : the simple, binary and the hybrid technique. Karatsuba multipliers in VHDL or verilog can be generated.
    [Download Karatsuba generator for VHDL].
    [Download Karatsuba generator for Verilog].

  • A tool to generate verilog code that finds the inverse of an element in a finite field. The algorithm used is a variant of the Itoh-Tsujii algorithm called quad-ITA. This algorithm is tuned for the FPGA platform. [ Download].


    • High Performance Elliptic Curve Crypto-Processor for FPGA Platforms, Chester Rebeiro and Debdeep Mukhopadhyay, 12th IEEE VLSI Design and Test Symposium, Bangalore, July 2008. [PDF].
    • Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier, Chester Rebeiro and Debdeep Mukhopadhyay, 21stIEEE Conference on VLSI Design, Hyderabad, January 2008. [Link].
    • Hybrid Masked Karatsuba Multiplier for GF(2233), Chester Rebeiro and Debdeep Mukhopadhyay, 11th IEEE VLSI Design and Test Symposium, Kolkata, August 2007. [PDF].