Overview

This research focuses on the effect of process scaling on power vulnerabilities. Scaling introduces variability, and this may have unexplored effects on security of embedded devices. With the scaling of devices, power models start deviate from the linear power models, like Hamming Weight and Hamming Distance. This leads to different results on the application of conventional Differential Power Attacks (DPA). Furthermore, profiling attacks may require different approach, as two devices will not have the same result on profiling. Moreover, issues like cross-talk brings in challenges for the countermeasures developed: as traditional analysis assumed that independent computations stay independent, however with the effect of cross-talks in nano-scaled devices these defences might be exposed, as they violate this inherent assumptions. These points, open up a new challenge: how to analyze the effect of scaling on security?

Downloads

  • A Presentation can be found here, summarizing the existing literature: here. The survey is ongoing, and we will keep on adding more materials and thoughts.
  • A tool flow using existing licensed tools at IIT Kharagpur, to analyze power vulnerabilities at RTL Level.
    [Download Tool Flow for DPA analysis at Verilog level.].
  • A tool flow for DPA analysis at SPICE level [ Download].
  • A tool flow for DPA analysis at Gate level [ Download].
  • A tool flow for DPA analysis at Layout Level [ Download].


    References

    • Mathieu Renauld, François-Xavier Standaert, Nicolas Veyrat-Charvillon, Dina Kamel, Denis Flandre: A Formal Study of Power Variability Issues and Side-Channel Attacks for Nanoscale Devices. EUROCRYPT 2011: 109-128 [PDF]


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