Synthesis/design of simple data paths and controllers, Concept of Processor design.
FPGA (Field Programmable Gate Array) Prototype
Please solve the daily assignments, as you shall be graded on your daily performance.
Assignments: 60 marks
Lab Examination: 40 marks
Grading Policy for the SPIM Assignments:
Logic Checking : 40 %
Program is properly terminated using system calls: 10 %
Interactive User Interface: 30 % marks
Explanatory Comments: 20 % marks
Getting Started with SPIM
SPIMS20: A MIPS R2000 Simulator
Installation of SPIM
Problem Sheet 1: Basic IO operation using SPIM
Lab Exam Question Paper