research
My research area is in the lines of "Devising Improved Test Techniques for NoC Based Memory Systems"
The abstract of my present work is as follows.
Abstract
Designers using bus based interconnect network in System-on-Chips (SOCs) often face difficulty related to bandwidth, signal integrity, and power dissipation of the chip. A new communication architecture called Network-on-Chip (NoC) was proposed to solve these issues. However, like all other SoCs, NoC based SoCs must also be tested for manufacturing defects. Since embedded memories are more prone to manufacturing defects than other type of on-chip circuits, my research focuses on devising improved techniques for technology-independent functional testing of memory cores interconnected using NoC targeting low area, power and low testing time. My research work has explored the following directions to gain improvements on the already existing test approaches for memory cores interconnected using NoC: 1. Test Architecture - In the research work, a distributed Memory BIST architecture is proposed which can test heterogeneous memory cores interconnected using NoC.The hybrid test technique and the distributed BIST achitecture allows the test of memory cores to be performed at much lesser time than those reported in literature. 2. Test Schedule - Based on the proposed NoC based MBIST architecture, a test schedule is developed to optimize test time as well as keep the test power within the power budget. 3. Re-using on chip circuitry for test purpose - A MBIST architecture has been proposed which re-uses the refresh circuit of DRAM in performing transparent March tests on the DRAM. The refresh re-use technique is extended for test of number of cores interconnected using NoC. Refresh re-use overcomes the requirement of additional Design For Testability (DFT) hardware. 4. Test of NoC infrastructure : The test techniques which re-use NoC to act as TAM for test of memory cores assume that the NoC is fault free. Thus, to ensure a fault free NoC, the NoC infrastructure must be tested for faults prior to use of it as TAM. Since FIFO buffers constitute maximum of the NoC infrastructure area, the test of NoC infrastructure must begin with test of the FIFO buffers. During my research work an on-line transparent test technique is explored that performs on-line for FIFO buffers present within the routers of the NoC infrastructure. The test performs active fault detection over entire FIFO buffers.