Proportional fair schedulers (Pfair, ERfair, EPDF, etc.) with their ability to provide strict rate-based execution progress guarantees for any feasible real-time task set on multiprocessors provide an effective strategy for scheduling independent real-time applications with various degrees of timeliness criticality and Quality of Service (QoS) requirements. Such applications cover a wide range from time-critical applications like automotive control to multimedia streams in embedded infotainment. However, in spite of their potential theoretical usefulness, actual implementations of these fair schedulers are limited mainly due to relatively high scheduling complexity, inter-processor task migration and cache-miss related overheads.

This research endeavors to develop a framework for fast, flexible fair algorithms that can work effectively under a variety of practical situations like limited power, overload, faults, etc. over a wide range of architectures.

Although there exists proportional fair schedulers that are optimal in terms of fairness accuracy, they generally suffer super constant scheduling complexities. On the other hand, there are O(1) complexity round-robin based algorithms, but they generally fail to provide good fairness and tardiness properties.

This research focused on the development of real-time low scheduling complexity proportional fair schedulers which provide high fairness accuracy and efficiently handle dynamic workloads.

The main objective was to get a real-world experience of a multitasking programming environment for a versatile RISC processor. We had developed a concurrent, time-sharing prototype OS for Donald E. Knuth's futuristic hypothetical RISC processor MMIX.

The project focussed on the development of software tool sets for embedded processor cores. This tool set includes tools for Software Development, Architecture Evaluation and Instruction Set Architecture (ISA) Verification. The aim is to provide tools (like Simulators) and systems software (like Assemblers, Linkers, Compilers and Debuggers) to speed up the development of new architectures and also allow rapid design space exploration. Our team has successfully delivered a complete tool suite for NSC's (National Semiconductor, USA) CRX processor.

This project aims to provide an automated penetration testing framework in order to analyze a computer network, scan for security vulnerabilities, report these vulnerabilities, and also recommend suggestions/workarounds to correct/patch the vulnerabilities found.

This project endeavors to develop a fault-tolerant hardware and software architecture for GM’s automotive electronic control systems.