CS676 : DIGITAL DESIGN VERIFICATION (3 1 0 4)

Detailed Syllabus:

Overview: Introduction to verification, Developing Verification strategies, Applying Verification strategies, E-standard Programming Constructs, RTL ports and interfaces, Modeling hardware interfaces with concurrency constructs, simulating testbenches using Fork-join, stimulus synchronization using conventional synchronization constructs like Mailboxes, Semaphores, regions and events.

Hardware Verification Languages: Fundamentals of HVLs, concurrency Issues, Class definitions and instantiations, tasks and functions, Concurrent techniques, Automatic Stimulus generation and randomized testing using HVLs, Building Transactors and Stubs, Result checking, Coverage and Regression, Debuggng

Advanced Functional Verification: RTL verification; Processor verification issues, functional verification using constraint modelling.

Basics of Formal Verification: Property Checking. Comparision with simulation based technique; Decision Diagrams, Use of CUDD

Summary: In this course we shall learn the following:

1. Verification Aims and Techniques

2. Simulation based verification

3. How to use Langauge e?

4. Basics of Formal Verification

Text Books:

Design Verification with 'e': By Samir Palnitkar.

Hardware Design Verification: Simulation and Formal Method-Based Approaches: By William K. Lam, Prentice Hall

Writing Testbenches using System Verilog: By Janick Bergeron, Springer

Presentations for the class:

Introduction to Verification.

Slides on Verilog.

Introduction (contd.)

The Specman Elite Tutorial : Verification using language 'e'.

Advanced Concepts in Simulation Based Verification.

Decision Diagrams and Equivalence Checking.

Assignments:

First Tutorial (submission deadline: 23.1.07)

Second Tutorial (submission deadline: 10.2.07)

Third Tutorial (submission deadline: 17.2.07)

Quizes and Questions:

First Quiz

Papers to Read:

An Overview on HDLs and HVLs

Extracting FSM Coverage using Specman (READ THIS AND PRACTISE IN THE LAB)

Laboratory:

Getting Started in 'e'

Verification of an arithmetic block to compute remainder of CRC-8

Transaction Level Test-Bench Writing

An Overview on Verilog Tasks and Functions

A Tutorial on Specman Elite