In the existing practice of railway signalling, especially in India, the route control chart (RCC) is prepared manually from the signal interlocking plan (SIP). Electronic interlocking (EI) is programmed with the data prepared manually from the RCC along with the relay circuit schematics by railway design engineers. These procedures are prone to human errors and can lead to violations of signalling safety which may cause for unfortunate incidents. As the number of routes increase for larger yards, the complexity of RCC and relay logic circuit preparation grow significantly. In this thesis, methods to reconcile the problems indicated above are described. Graph-based representation has been used to capture a SIP using a tool with a suitable graphical user interface. Graph traversals are performed to extract a variety of information for RCC generation. Algorithms have been developed and analysed for route identification, overlap identification, route conflict identification, route isolation. Thereafter, logic generation is carried out using railway specified standard circuit schematics. These are represented in XML using suitably defined iterator constructs. Iterators are used to extract the relay specific information using suitable queries. Finally, formal methods are applied for yard layout validation and logic circuit verification. Necessary safety properties for yard validation and logic verification have been coded in LTL. Models have been developed based on the graph representation of the yard and the relay logic definitions. The NuSMV model checker has been used. A number of subsidiary tasks have also been carried out, such as GUI development for SIP capture and a rendering mechanism to display ladder logic circuits equivalent to relay logic circuits. All tools and techniques have been satisfactorily tested on actual railway yards.