1. Design of perfect circuit - 10
2. Design of all faulty modules + MUX - 10
3. Test Bench Generation as per given probabilities - 20
4. Report - 10
1. Problem 1 - 20
2. Problem 2 - 20
3. Problem 4,5 - 20
4. Problem 6 - 20
--In each part, marks is given based on program functionality, programming elegance and proper documentation.
1. Implementation of different cache functionalities - 40
2. Implementation of Fault Injection - 20
3. Deriving results for traces provided - 20
4. Plotting results and proper documentation - 20