**Multiobjective Heuristic Search**by Dasgupta, P., Chakrabarti, P.P. and De Sarkar, S.C.

Vieweg Verlag, Germany and Morgan Kaufmann, USA, 1999 (ISBN: 978-3-5280-5708-4).**Cohesive Coverage Management Leveraging Formal Test Plans**by Aritra Hazra, Pallab Dasgupta and Partha Pratim Chakrabarti

Lap Lambert Academic Publishing, GmbH, Germany, 2012 (ISBN: 978-3-8473-7645-3).**Static Analysis and Optimization of Object Oriented Systems – Concepts and Approaches**by Soham S. Chakraborty, Rajeev Kumar and P. P. Chakrabarti

Lap Lambert Academic Publishing, GmbH, Germany, 2012 (ISBN: 978-3-8484-1353-9).**Method and Apparatus for Extracting Assume Properties**by Kaushik De, Edward Cerny, Pallab Dasgupta, Bhaskar Pal, P. P. Chakrabarti

US Patent No.: 7,797,123 dated Sep. 13, 2010.**Method and Apparatus for Operational-Level Functional and Degradation Fault Analysis**by Dipankar Das, P. P. Chakrabarti, Purnendu Sinha

US Patent No.: 8,108,728 dated Jan. 30, 2012.**Heuristic search through islands**by Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

Artificial Intelligence, vol.29, pp.339-347, 1986.**Distance Functions in Digital Geometry**by Das, P.P., Chakrabarti, P.P., Chatterjee, B.N.

Information Sciences, 42 (1987) pp 113 - 136.**Generalized Distance in Digital Geometry**by Das, P.P., Chakrabarti, P.P., Chatterjee, B.N.

Information Sciences, 42 (1987), pp. 51 - 67.**Admissibility of AO* when heuristics overestimate**by Chakrabarti, P.P., Ghose, S. and DeSarkar, S.C.

Artificial Intelligence , 34(1988), pp. 97 - 113.**IODYS - A Prototype Software for Computer Aided Policy Design**by Ghose, S., Chakrabarti, P.P.

System Dynamics : an International Journal of Policy Modelling, 2(2), 1989, pp 9-26.**An architecture for an intelligent software environment for policy design in System Dynamics models**by Ghose, S., Chakrabarti, P.P.

System Dynamics: an International Journal of Policy Modelling, 2(2), 1989, pp 1 - 8.**Increasing search efficiency using multiple heuristics**by Chakrabarti, P.P., Ghose, S., Pandey, A., DeSarkar, S.C.

Information Processing Letters 30(1989), pp 33 - 36.**Heuristic search in restricted memory**by Chakrabarti, P.P., Ghose, S., Acharya A. and DeSarkar, S.C.

Artificial Intelligence 41 (1989/90) pp 197 - 221.**Automatic Generation of Programs from recursive definitions for combinatorial problems**by Chakrabarti, P.P., Ghose, S. and Bakre, A.

Vivek, 3(4), 1990, pp 3 - 15.**The t-Cost-m-Neighbour Distance in Digital Geometry**by Das, P.P., Chakrabarti, P.P., Chatterjee, B.N.

Journal of Geometry, 42(1991), pp 42 - 58**Reducing re-expansions in iterative-deepening search by controlling cutoff bounds**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., De Sarkar, S.C.

Artificial Intelligence. 50(1991) pp 207 - 221.**Allocation of registers to multiport memories based on register-interconnect optimization**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

Modelling and Simulation, 25(4), 1991, pp 57 - 64.**Multiple stack branch and bound**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., De Sarkar, S.C.

Information Processing Letters, 37, 1991, pp 43 - 48.**Register-interconnect optimization in data path synthesis**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

Microprocessing and Microprogramming, 33 (1991/2) 279 - 288.**Generalized best first search using single and multiple heuristics**by Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

Information Sciences, 60(1-2), pp 145-175, 1992.**A generalized AND/OR graph search algorithm**by Chakrabarti, P.P., Ghose, S.

Journal of Algorithms, 13(1992), pp 177 - 187.**Qualitative Description of Three-dimensional scenes**by Biswas, P.K., Mukherjee, J., Chatterjee, B.N., Chakrabarti, P.P.

Int. Journal of Pattern Recognition and Artificial Intelligence, 6 (1992) 651 - 672.**The Towers of Hanoi: Generalizations, Specializations and Algorithms**by Gupta, P., Chakrabarti, P.P., Ghose, S.

Int. Journal of Computer Math., 46 (1992) p 149 - 161.**A simple 0.5-bounded greedy algorithm for the 0/1 knapsack problem**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

Information Processing Letters, 42(1992), pp 173-177.**The Effective use of Memory in Iterative Deepening Search**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

Information Processing Letters, 42(1992), pp 47 - 52.**Heuristic Search**by Chakrabarti, P.P.

Physics News, 1992.**Agent Searching in a Tree and the optimality of Iterative deepening**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Artificial Intelligence 71(1994) 195 - 208.**Improving Greedy Algorithms by Lookahead Search**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., De Sarkar, S.C.

Journal of Algorithms, 16,(1994), pp 1 - 23.**Algorithms for searching explicit AND/OR graphs and their applications to problem reduction search**by Chakrabarti, P.P.

Artificial Intelligence 65 (1994), pp 329 - 345.**A Correction to Agent Searching in a Tree and the optimality of Iterative deepening**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Artificial Intelligence 77(1995) 173-176.**Utility of Pathmax in Partial Order Heuristic Search**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Information Processing Letters 55(1995) 317-322.**EARTH: Combined State Assignment of PLA-based FSM's Targeting Area and Testability**by Rama Mohan, C., Chakrabarti, P.P.

IEEE Transactions on Computer Aided Design, 15, 7 (1996), pp 727 - 731.**Agent Searching in uniform b-ary trees: Multiple Goals and Unequal Costs**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Information Processing Letters, 58, (1996) pp 311 - 318.**Learning for Efficient Search**by Sarkar, S., Ghose, S., Chakrabarti, P.P.

Sadhana, Spl. Issue on Intelligent Systems, 21, 3 (1996) pp 291 - 315.**Heuristic Search Strategies for Multiobjective State Space Search**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Sadhana, Spl. Issue on Intelligent Systems, 21, 3 (1996) pp 263 - 290.**Multiobjective Heuristic Search in AND/OR Graphs**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Journal of Algorithms 20, (1996) pp 282 - 311.**Searching Game Trees under a Partial order**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

Artificial Intelligence 82 (1996) pp 237 - 257.**Resultant Projection Neural Networks for Optimization Under Inequality Constraints**by Vinod, V.V., Ghose, S, Chakrabarti, P.P.

IEEE Transactions On Systems, Man and Cybernetics 26, 4 (1996) pp 509 - 521.**Factorizing FSM's with Modify and Restore Method**by Rama Mohan, C., Chakrabarti, P.P.

IEEE Transactions on Circuits Systems, Part II 44, 5 (1997), pp 371 - 377.**A Probabilistic Estimator for the Vertex Deletion Problem**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

Journal of Computers and Mathematics with Applications, 35,6 , pp 1-4 (1998).**Some New Results in the Complexity of Allocation Sub-problems in Datapath Synthesis**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

International Journal of Computer Mathematics with Applications, vol 35 (10), pp 93 - 105, 1998.**Complexity of Scheduling in High Level Synthesis**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

VLSI Design Journal, vol 7, No. 4, pp 337-346, 1998.**Complexity of Fragmentable Object Bin Packing and an Application**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

Journal of Computer and Mathematics with Applications, vol 35(11) pp 91 - 97, 1998.**A Framework and Algorithms for Learning in Search Based Systems**by Sarkar, Sudeshna, Chakrabarti, P.P., Ghose, Sujoy.

IEEE Trans. on Knowledge Data Engineering, Vol. 10, No. 4, July/August 1998, pp 563 - 575.**Learning While Solving Problems in Best First Search**by Sarkar, Sudeshna, Chakrabarti, P.P., Ghose, Sujoy.

IEEE Transactions of Systems, Man & Cybernetics, Part A, Vol. 28, No. 4, July 1998, pp. 535--542.**A Design Space Exploration Scheme for Datapath Synthesis**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

IEEE Transactions in VLSI Systems, 7(3), 1999 pp 331-338.**Partial Precedence Constrained Scheduling**by Chakrabarti, P.P.

IEEE Transactions on Computers, 48 (10), 1999, pp 1127 - 1130.**Solving Multiple Processor and Multiple Resource Constrained Scheduling Problems using a Genetic Algorithm Approach**by Hussain, S.A., Chakrabarti, P.P. and Sastry, V.U.K.

Int. Journal. On Computer Mathematics 75 (1): 21-40 2000.**Model Checking of Timed Event Structures**by Dasgupta, P., Deka, J. K., Chakrabarti, P.P.

IEEE Transactions on Computer-Aided Design, 19(5) May 2000 pp 601 - 611.**GABIND: A Genetic Algorithm Approach to Allocation and Binding for the High-Level Synthesis of Data Paths**by Mandal, C. A., Chakrabarti, P. P., Ghose, S.

IEEE Transactions on VLSI System Design, 8(6), pp 747 - 750, (2000).**Min-Max Computation Tree Logic**by Dasgupta, P., Chakrabarti, P.P., Deka, J.K., Shankarnarayanan, S.

Artificial Intelligence, 127(1), pp 137 - 162 (2001).**Solving Constraint Optimization Problems from CLP-Style Specifications using Heuristic Search Techniques**by Dasgupta, P., Chakrabarti, P.P., Dey, A., Ghose, S and Bibel, W.

IEEE Transactions on Knowledge Data Engineering 14(2), pp 353 - 368, 2002.**Min-Max Event Triggered Computation Tree Logic**by Deka, J. K., Dasgupta, P., Chakrabarti, P.P.

Sadhana (Vol 27, 2, pp: 163 - 180, 2002).**Quantified Computation Tree Logic**by Patthak, A.C., Bhattacharya, I., Dasgupta, A., Dasgupta, P., Chakrabarti, P.P.

Information Processing Letters, 82(3): 123-129, 2002.**Agent Searching**by Dasgupta, P., Chakrabarti, P.P., DeSarkar, S. C.

Computational Mathematics, Modelling and Algorithms, Narosa Publishing House, New Delhi, 2002, 397- 444.**Genetic Algorithms for High-Level Synthesis in VLSI Design**by Mandal, C, Chakrabarti, P.P.

Materials and Manufacturing Processes, 18(3), pp 355 - 383, 2003.**A branching time temporal framework for quantitative reasoning**by Chatterjee, K., Dasgupta, P., Chakrabarti, P. P.

Journal of Automated Reasoning, 30: 205-232, 2003.**The power of first-order quantification over states in branching and linear time temporal logics**by K. Chatterjee, P. Dasgupta, P. P. Chakrabarti

Information Processing Letters Elsevier 91, 201-210 (2004).**A synthesis system for analog circuits based on evolutionary search and topological reuse**by T. R. Dastidar, P. P. Chakrabarti, P. Ray

IEEE Transactions on Evolutionary Computation 9(2), 211-224, April (2005).**Post-compilation optimization for multiple gains with pattern matching**by Rajeev Kumar, Amit Gupta, BS Pankaj, Mrinmoy Ghosh, and PP Chakrabarti

ACM SIGPLAN Notices 40 (12): 14 - 23, December 2005.**A framework for systematic validation and debugging of pipelined simulators**by Arnab Roy, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti

ACM Transactions on Design Automation of Electronic Systems Association for Computing Machinery (ACM) 10(3), 462-491, July (2005).**Prediction of Properties of Rubber Using Artificial Neural networks**by Vijayabaskar, V., Gupta, R., Chakrabarti, P. P., Bhowmik, Anil. K.

Journal of Applied Polymer Science, Vol 100, pp 2227 - 2237 (2006).**Moving Sound Reduces Arousal in Psychosomatic Patients**by Bandopadhyay Sajal, Mandal Manas K, Chakrabarti Partha P, Ghatak Sobhendu K, Chowdhury Raghabendra, Ray Swagata

International Journal of Neurosciences, 116(8), pp 915 - 920, 2006.**Design Intent Coverage - A New Paradigm for Formal Property Verification**by Basu, P., Das, S., Banerjee, A., Dasgupta, P., Chakrabarti, P.P., Mohan, C.R., Fix L., Armoni, R.

IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems, 25 (10), pp 1922 - 1934, 2006.**Reasoning about Timing Behavior of Digital Circuits using Symbolic Event Propagation and Temporal Logic**by Mondal Arijit, P. P. Chakrabarti

IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems, 25 (9), pp 1793 - 1814, 2006.**Frame-based Proportional Round Robin**by Sarkar, Arnab, Chakrabarti, P. P., Kumar Rajeev

IEEE Transactions on Computers, 55(9), pp 1121 - 1129, 2006.**BUSpec: A Framework for Generation of Verification Aids for Standard Bus Protocol Specifications**by Pal, B., Banerjee, A., Dasgupta, P., Chakrabarti, P.P.

Integration, the VLSI Journal, 40, pp 285-304, 2007.**An Evolutionary Algorithm based approach to Automated Design of Analog and RF circuits using Adaptive Normalized Cost Functions**by Somani, A., Chakrabarti, P. P., Patra, A.

IEEE Transactions on Evolutionary Computing, 11(3), pp 336-353, 2007.**An Automated meta-Level Control Framework for Optimizing the Quality-Time Trade-off of VLSI Algorithms**by Aine, Sandip, Chakrabarti, P.P., Kumar Rajeev

IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems, 26(11), pp 1992 -2008, 2007.**A Verification System for Transient Response of Analog Circuits**by Dastidar, T.R, Chakrabarti, P.P.

ACM Transactions on Design Automation of Electronic Systems, 12 (3), 39 pages, 2007.**Event Propagation for Accurate Circuit Delay Calculation using SAT**by Roy Suchismita, Chakrabarti, P.P., Dasgupta, P.

ACM Transactions on Design Automation of Electronic Systems, 12(3), 23 pages, 2007.**Statistical Static Timing Analysis using Symbolic Event Propagation**by Mondal Arijit, Chakrabarti, P.P., Dasgupta Pallab

IET Journal on Computers and Digital Techniques, 1(4), pp 283 - 291, 2007.**Hardware Accelerated Random Test Generation**by Pal Bhaskar, Sinha Arnab, Dasgupta Pallab, Chakrabarti, P. P., De Kaushik

IET Journal on Computers and Digital Techniques, 1(4), 423-433, 2007.**Functional Verification of Task Partitioning for Multiprocessor Embedded Systems**by Das, Dipankar, Chakrabarti, P.P., Kumar Rajeev

ACM Transactions on Design Automation of Electronic Systems, 12(4), 53 pages, 2007.**Satisfiability Models for Maximum Transition Power**by Roy Suchismita, Chakrabarti, P. P., Dasgupta, P.

IEEE Transactions on VLSI Systems, 16(8), 941-951, 2008.**Hybrid Scheduling of Dynamic Task Graphs with Selective Duplication for Multiprocessors under Memory and Time Constraints**by Choudhury Pravanjan, Kumar Rajeev , Chakrabarti P. P.

IEEE Transactions on Parallel and Distributed Systems, 19(7), 967-980, 2008.**Simulation-based verification using Temporally Attributed Boolean Logic**by Panda S. K., Roy Arnab , Chakrabarti P. P., Kumar Rajeev

ACM Transactions on Design Automation of Electronic Systems, 13(4), 52 pages, 2008.**Auxiliary state machines + context-triggered properties in verification**by Banerjee Ansuman, Dasgupta Pallab, Chakrabarti P. P.

ACM Transactions on Design Automation of Electronic Systems, 13(4), 31 pages, 2008.**Design intent coverage revisited**by Sinha Arnab, Dasgupta Pallab, Pal Bhaskar, Das Sayantan, Basu Prasenjit, Chakrabarti P. P.

ACM Transactions on Design Automation of Electronic Systems, 14(1), 32 pages, 2009.**Adaptive parameter control of evolutionary algorithms to improve quality-time trade-off**by Aine Sandip, Kumar Rajeev, Chakrabarti, P.P.

Applied Soft Computing 9(2): 527-540, 2009.**Scenario-based Timing Verification of Multiprocessor Embedded Applications**by Das, Dipankar, Chakrabarti, P.P., Kumar Rajeev

ACM Transactions on Design Automation of Electronic Systems, 14(3), 58 pages, 2009.**Thermal Analysis of Multiprocessor SoC Applications by Simulation and Verification**by Das, Dipankar, Chakrabarti, P.P., Kumar Rajeev

ACM Transactions on Design Automation of Electronic Systems, 12(2), 52 pages, 2010.**Partition-Oriented Frame Based fair Scheduler**by Sarkar Arnab, Ghose, S, Chakrabarti, P.P.

Journal of Parallel and Distributed Computing, (70), 707-718, 2010.**Bounded Delay Timing Analysis and Power Estimation using SAT**by Roy Suchismita, Chakrabarti, P.P., Dasgupta Pallab

Microelectronics Journal (Elsevier) 41(5), 317 - 324, 2010.**Heuristic Search under Contract**by Sandip Aine, P P Chakrabarti, and Rajeev Kumar

Computational Intelligence, 26 (4), 386 - 419, 2010.**MAWA* - A Memory Bounded Anytime Heuristic Search Algorithm**by Satya Gautam Vadlamudi, Sandip Aine, P P Chakrabarti

IEEE Transactions on Systems, Man and Cybernetics, Part B, 41(3), pp 725-735, 2011**A Low Overhead Partition Oriented ERFair Scheduler for Hard Real-Time Embedded Systems**by Arnab Sarkar, Amit Shanker, S Ghose, P P Chakrabarti

IEEE Embedded Systems Letters, 3(1), 5-8, March 2011**Sticky-ERFair: A Task-Processor Affinity Aware Proportional Fair Scheduler**by Arnab sarkar, Sujoy Ghose, P P Chakrabarti

Real-Time Systems 47(4), 356-377 2011.**A Corrigendum to Sticky-ERFair: A Task-Processor Affinity Aware Proportional Fair Scheduler**by Arnab sarkar, Sujoy Ghose, P P Chakrabarti

Real-Time Systems 47(4), 382-385 2011.**Online Scheduling of Dynamic Task Graphs with Communication and Contention for Multiprocessors**by Pravanjan Choudhury, P P Chakrabarti, Rajeev Kumar

IEEE Transactions on Parallel & Distributed Systems, 23 (1) 126-133 2012.**A dynamic assertion-based verification platform for validation of UML designs**by Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, P. P. Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan

ACM SIGSOFT Software Engineering Notes 37(1): 1-14 (2012).**SAT based Timing Analysis for Fixed and Rise/Fall Gate Delay Models**by Suchismita Roy, P P Chakrabarti, Pallab Dasgupta

Integration, The VLSI Journal 45(4): 357-364 (2012)**Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures**by Priyankar Ghosh, Amit Sharma, P. P. Chakrabarti, Pallab Dasgupta

Journal of Artificial Intelligence Research Vol 44, pp 275-333, 2012**Cohesive Coverage Management: Simulation meets Formal Methods**by Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, P. P. Chakrabarti

Journal of Electronic Testing: Theory and Applications 28(4), 449-468, (2012)**Symbolic Event Propagation Based Minimal Test Set Generation for Robust Path Delay Faults**by Arijit Mondal, P P Chakrabarti, Pallab Dasgupta

ACM Transactions on Design Automation of Electronic Systems, 17(4): 47 (2012)**Formal Methods for Early Analysis of Functional Reliability in Component-Based Embedded Applications**by Aritra Hazra, Priyankar Ghosh, S. G. Vadlamudi, P. P. Chakrabarti, Pallab Dasgupta

IEEE Embedded Systems Letters, vol.5, no.1, pp.8-11, Mar. 2013.**Incremental Beam Search**by S. G. Vadlamudi, Sandip Aine, P. P. Chakrabarti

Information Processing Letters (IPL), Elsevier, vol.113, no.22-24, pp.888-893, Nov.-Dec. 2013.**Robustness Analysis of Embedded Control Systems with respect to Signal Perturbations: Finding Minimal Counterexamples using Fault Injection**by S. G. Vadlamudi, P. P. Chakrabarti

IEEE Transactions on Dependable and Secure Computing (TDSC), vol.11, no.1, pp.45-58, Jan.-Feb. 2014.**An architecture Intelligent DSS using System Dynamics models**by Ghose, S., Chakrabarti, P.P., Bapna, R.K.

2nd National on System Dynamics, Varanasi, 1987.**Qualitative Optimization: an AI approach to policy design in System Dynamics**by Ghose, S., Chakrabarti, P.P., Jain, S., Dubey, R.K.

2nd National Conf. on System Dynamics, Varanasi, 1987.**Tree searching in restricted memory**by Chakrabarti, P.P., Ghose, S., Acharya Arup, DeSarkar, S.C.

International Symp. On ELDECS, Kharagpur, India, pp.518 - 520, 1987.**Best first search in AND/OR graphs**by Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

16th ACM Computer Science Conference, Atlanta, USA, pp. 256 - 261, 1988.**Pruning by upper bounds in heuristic search: use of approximate algorithms**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

Knowledge Based Computer Systems (KBCS), Narosa Publishing House, pp 451 - 461, 1990.**Controlling Re-expansions in Iterative Deepening Search**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S., DeSarkar, S.C.

Prof. A.K. Chaudhuri Commemoration Conference (PARCOM), Calcutta, Feb 1990.**Solving multidimensional knapsack problems using Neural networks**by Vinod, V.V., Ghose, S., Chakrabarti, P.P.

PARCOM 90, Pune, India, Dec 1990.**Learning the topology of a feed forward neural network from examples**by Vinod .V, Ghose, S., Chakrabarti, P.P.

KBCS 90, Pune, India, Dec 1990.**Neural Networks -Review and Applications**by Chakrabarti, P.P.

National Seminar on Parallel Computer Systems and Applications, Calcutta, India, Oct. 1990.**Reducing the selection overhead in a best first search scheme**by Sarkar, U.K, Chakrabarti, P.P., Ghose, S, De Sarkar, S.C.

KBCS 90, Pune, India, Dec 1990.**The Towers of Hanoi Revisited**by Gupta, P., Chakrabarti, P.P., Ghose, S

Theoretical CS Conf., Madras, 1991.**Artificial Intelligence Models**by Chakrabarti, P.P.

Indian Science Congress, Baroda, Jan 1992.**A new algorithm for PLA folding**by Rama Mohan, C., Chakrabarti, P.P., Ghose, S.

Int. Conf. on VLSI Design 1992, Bangalore, Jan 1992.**Interconnect Optimization Techniques in Data Path Synthesis**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

VLSI 92, Bangalore, Jan 1992.**Learning to Search Efficiently using Multiple Heuristic Functions**by Sarkar, S., Chakrabarti, P.P., Ghose, S

3rd Symposium on Intelligent Systems, Bangalore, Nov, 1993.**A Learning System for Plane Geometry Problem Solving**by Sarkar, S., Ghose, S., Chakrabarti, P.P.

International Computing Congress, Hyderabad, 1993.**Multiple Output Function Realisation using Folded 3-level PLA's**by Rama Mohan, C., Chakrabarti, P.P., Ghose, S.

International Computing Congress, Hyderabad, 1993.**Heuristic Search using Multiple Objectives**by Dasgupta, P., Chakrabarti, P.P.

3rd National Seminar on Theor. CS, 1993.**Some New Results in Heuristic Search**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S.

3rd National Seminar on Theor. CS, 1993.**Greedy Lookahead Search**by Sarkar, U.K., Chakrabarti, P.P., Ghose, S.

3rd National Seminar on Theor. CS, 1993.**Combining PLA folding with state Assignment**by Rama Mohan, C., Chakrabarti, P.P., Ghose, S

Int. Conf. on VLSI Design, Bombay, 1993.**Multiobjective Search in VLSI Design**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

VLSI 94 International Conf. on VLSI Design 1994.**A New Method for Synthesis of PLA Based FSM's**by Rama Mohan, C., Chakrabarti, P.P.

VLSI 94, International Conf. on VLSI Design 1994.**A New Approach for Factorizing FSM's**by Rama Mohan, C., Chakrabarti, P.P.

ICCAD 94 (ACM/IEEE International Conf on CAD), 1994.**Complexity of Scheduling Two Operation Chains and Some Other Related Problems**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

4th National Seminar on Theoretical Computer Science, Kanpur, 1994.**Game Tree Search Under a Partial Order**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

4th National Seminar on Theoretical Computer Science, Kanpur, 1994.**Continuous Learning of the Distribution of Heuristic Estimates While Solving Problems**by Sarkar, S., Chakrabarti, P.P., Ghose, S.

4th National Seminar on Theoretical Computer Science, Kanpur, 1994.**Learning to Solve Problems in Best-First Search**by Sarkar, S., Chakrabarti, P.P., Ghose, S.

International Workshop on Artificial Intelligence, Calcutta, 1994.**Multiobjective Heuristic Search Methods**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

International Workshop on Artificial Intelligence, Calcutta, 1994.**A Framework for High Level Synthesis**by Mandal, C.A., Chakrabarti, P.P., Ghose, S

International Workshop on Artificial Intelligence, Calcutta, 1994.**State Assignment for PLA-based FSM's targeting area and testability**by Rama Mohan, C. and Chakrabarti, P.P.

VLSI 95, 8th International Conference on VLSI, New Delhi, 1995.**Allocation of Registers to Multi-port Memories Based on Register--Interconnect Optimization**by Mandal, C. A., Chakrabarti, P. P., Ghose, S.

ICAUTO International Conference- 1995, Indore, pp. 611-614, 1995.**A near optimal algorithm for the extended cow-path problem**by Dasgupta, P., Chakrabarti, P.P., De Sarkar, S.C.

FSTTCS, 1995, Lecture Notes in Computer Science vol 1026, pp 22 - 36.**Port Assignment of dual and triple port memories using a genetic approach**by Mandal, C.A., Chakrabarti, P.P., Ghose, S.

APCHDL 96, Bangalore, 1996.**A new competitive algorithm for agent searching in unknown streets**by Dasgupta, P., Chakrabarti, P.P. and De Sarkar, S.C.

FSTTCS, 1996, Lecture Notes in Computer Science vol 1180, pp 147 - 155.**Allocation and Binding for Datapath Synthesis using a Genetic Approach**by Mandal, C.A, Chakrabarti, P.P. and Ghose, S

VLSI 96 9th International Conference on VLSI, Bangalore, 1996.**Polynomial Time Lookahead Based Heuristic Search Algorithms**by Sarkar, S., Chakrabarti, P.P. and Ghose, S.

KBCS 96, Mumbai 1996.**Design Space Exploration in High Level Synthesis**by Mandal, C.A., Chakrabarti, P.P. and Ghose, S.

VLSI 97, 9th International Conference on VLSI Design, Hyderabad, 1997.**A Heuristic Search Approach to Effectively Solve Constrained Optimization Problems from Logical Specifications**by Dasgupta, P., Chakrabarti, P.P., Ghose, S., Dey, A. and Bibel, W.

KBCS-98, Mumbai 1998.**IMIS: A Tool for Development of MIS for Internet / Intranet Environment**by Chakrabarti, P.P., Singh A.K., and Rai, S.

Tencon-98, 1998.**Controlling State Explosion in Static Simulation by Selective Composition**by Chakrabarti, P.P., Dasgupta, P., Das, P.P., Roy A., Lahiri, S. and Bose, M.

VLSI Design 99 12th International Conference on VLSI Design, Goa, Jan 1999.**Exploiting Isomorphism for Compaction and faster Simulation of Binary Decision Diagrams**by Chauhan, P., Dasgupta, P and Chakrabarti, P.P.

VLSI Design99 12th International Conference on VLSI Design, Goa, Jan 1999.**An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays**by Deka, J.K., Dasgupta, P. and Chakrabarti, P.P.

VLSI Design99 12th International Conference on VLSI Design, Goa, Jan 1999.**Specification of Planning Goals in Branching Time Logics in Stochastic Systems**by Sarkar, S., Chakrabarti, P.P., Dasgupta, P., Niyogi, R.

KBCS-2000, December 2000.**A Comparative Analysis of BDD-Based and Rule-Based Reachability Problems for Cellular Automata**by Deka, J.K., Dasgupta, P., Chakrabarti, P.P.

ICCCD 2000, India, December 2000.**Verification of Concurrent Communicating Systems in Boolean SDL**by Patthak, A.C., Bhattacharyya, I., Dasgupta, A., Chakrabarti, P.P., Dasgupta, P.

Conference on Intelligent Computing and VLSI, pp 115 - 122, Kalyani, India, February 2001.**Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions**by Dasgupta, P., Chakrabarti, P.P., Nandi, A., Krishna, S., Chakrabarti, A.

DATE 2001, Munich, March 2001.**Abstractions for Model Checking of Event Timings**by J.K. Deka, S. Chaki, Pallab Dasgupta, and P.P. Chakrabarti

ISCAS 2001: IEEE Int. Symp. On Circuits and Systems, Sydney, Australia, 2001.**Symbolic verification of Boolean constraints over partially specified functions**by Sriram, R. Tandon, Pallab Dasgupta, and P.P. Chakrabarti

ISCAS 2001: IEEE Int. Symp. On Circuits and Systems, Sydney, Australia, 2001.**Specification of Planning Goals using Automata theoretic approaches**by S. Sarkar, P. P. Chakrabarti, R. Neogi

CIT'01: International Conf. On Information Technology, India, December, 2001.**Weighted Quantified Computation Tree Logic**by Chatterjee, P. Dasgupta and P.P. Chakrabarti

CIT'01: International Conf. On Information Technology, India, December, 2001.**Open Computation Tree Logic for Formal Verification of Modules**by P. Dasgupta, A. Chakrabarti, P.P. Chakrabarti

ASPDAC / VLSI Design 2002: ACM/IEEE Joint Conference of Asia Pacific Design Automation Conference and VLSI Design Conference, 2002.**Formal Verification of Module Interfaces against Real Time Specifications**by Chakrabarti A, P. Dasgupta, P.P. Chakrabarti and A. Banerjee

Design Automation Conference (DAC 2/002), New Orleans, 2002.**Timing Analysis of Tree-like RLC Circuits**by B. Rajendran, V. Kheterpal, A. Das, J. Majumder, C. Mandal. C, P.P. Chakrabarti

ISCAS 2002, USA, May 2002.**Open Computation Tree Logic with Fairness**by Banerjee A., Dasgupta, P., and Chakrabarti, P.P.

ISCAS 2003, Bangkok, 2003.**An algorithm for the extraction of DNA fragments using restriction enzymes**by Das, Kaustav, Dasgupta, P, Chakrabarti, P.P.

6th International Conference on Information Technology, Bhubaneswar, India, December 2003.**Code compression for RISC processors with variable length instruction encoding**by S.S. Gupta, D. Das, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti

Int. Conf. High Performance Computing (HIPC), Hyderabad. 17-20 December 2003.**Estimating buffer limits in communicating concurrent producer-consumer systems**by S. Das, P. Dasgupta, P.P. Chakrabarti

CIT'2003, Bhubaneswar, 2003.**Formal Verification of Modules under Untimed and Real Time Fairness Constraints**by Banerjee, A, Dasgupta, P., Chakrabarti, P.P.

VLSI '2004, India, 2004.**Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?**by Basu Prasenjit, Das Sayantan, Dasgupta P., Chakrabarti P.P, Chunduri Rama Mohan, Fix Limor

DATE2004: page 668-669, 2004.**A New Approach to Timing Analysis Using Event Propagation and Temporal Logic**by Mondal, A., Chakrabarti, P.P. Mandal, C.R.

Design, Automation and Test in Europe Conference and Exposition (DATE 2004): page - 1198-1203, 2004.**Formal Verification Coverage: Computing the Coverage Gap between Temporal Specifications**by S. Das, P. Basu, A. Banerjee, P. Dasgupta, P.P. Chakrabarti, C.R. Mohan, L. Fix, R. Armoni

ACM/IEEE ICCAD'2004, pp 198 - 203, San Jose, California. 2004.**An Assertion-based Language for Generating Test Sequences for Complex Temporal Behavior**by P. Roy, P. Dasgupta, P.P. Chakrabarti

VDAT'2004, Mysore, 2004.**A Simulation Coverage Metric for Analyzing the Behavioral Coverage of an Assertion Based Verification IP**by B. Pal, A. Banerjee, K. Chaitanya, P. Dasgupta, P.P. Chakrabarti

VDAT'2004, Mysore, 2004.**Design Issues for Assertion-Based Verification IPs: The OVA Experience**by A. Banerjee, B. Pal, P. Dasgupta, P.P. Chakrabarti, M. Jha. E. Cerny

SNUG'2004, Bangalore, 2004.**Formal Verification of Modules under Real-Time Environment Contraints**by A. Banerjee, P. Dasgupta, P.P. Chakrabarti

IEEE VLSI Design'2004, Mumbai, 2004.**Property Refinement Techniques for Enhancing Coverage of Formal Property Verification**by P. Basu, P. Dasgupta, P.P. Chakrabarti, C.R. Mohan

IEEE VLSI Design'2004, Mumbai, 2004.**The BUSpec Platform for Automated Generation of Verification Aids for Standard Bus Protocols**by B. Pal, A. Banerjee, P. Dasgupta, P.P. Chakrabarti

IEEE MEMOCODE'2004, San Diego, California, 2004.**Complexity of Compositional Model Checking of Computation Tree Logic on Simple Structures**by K. Chatterjee, P. Dasgupta, P.P. Chakrabarti

6th International on Workshop Distributed Computing (IWDC), Kolkata, India, 27/12/2004, 102-113, Springer (LNCS 3326), 2004.**Assertion-based Verification: Have I written Enough Properties?**by Banerjee, B. Pal, K. Chaitanya, P. Dasgupta, P.P. Chakrabarti, M. Jha

IEEE Indicon 2004, Kharagpur, India, 20/12/2004, 363-367, IEEE, 2004.**Code compression using unused encoding space for variable length instruction encodings**by Dipankar Das, Rajeev Kumar, and PP Chakrabarti

8th VLSI Design & Test Workshop (VDAT), Mysore, August 2004.**Multiobjective genetic search for spanning tree problem**by Rajeev Kumar, PK Singh, P. P. Chakrabarti

11th International Conference on Neural Information Processing (ICONIP), Kolkata, India, 12/11/2004, 218-223, Springer (LNCS 3316), 2004.**Distributed evolutionary algorithm search for multiobjective spanning tree problem**by Rajeev Kumar, P. K. Singh, P. P. Chakrabarti

6th International on Workshop Distributed Computing (IWDC), Kolkata, India, 27/12/2004, 538, Springer (LNCS 3326), 2004.**SystemC modeling of a pipelined RISC processor based system**by Dipankar Das, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti

Performance Issues in Mobile Devices Workshop, Co-located with 11th HiPC, Bangalore, India, 17/12/2004, Web Procs., 2004.**Optimizing binaries for multiple gain factors using state-based model**by S. Pankaj, Amit Gupta, Rajeev Kumar, and P. P. Chakrabarti

Performance Issues in Mobile Devices Workshop, Co-located with 11th HiPC, Bangalore, India, 17/12/2004, Web Procs., 2004.**Improved quality of solutions for multiobjective spanning tree problem using evolutionary algorithm**by Rajeev Kumar, P. K. Singh, P. P. Chakrabarti

11th International Conference on High Performance Computing (HiPC), Bangalore, India, 17/12/2004, 494-503, Springer (LNCS 3296), 2004.**Syntactic Transformation of Assume-Guarantee Assertions: From Sub-modules to Modules**by P. Basu, P. Dasgupta, P.P. Chakrabarti

18th International Conference on VLSI Design, Kolkata, India, 3/1/2005, IEEE Computer Science Press, 2005.**Scoreboard Directed Dynamic Constraint Modification for Higher Simulation Coverage**by Pal, A. Nandi, S. Ray, A. Banerjee, P. Dasgupta, P. P. Chakrabarti

SNUG 2005, Bangalore, India, 25/5/2005, , , 2005.**Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model**by S. Das, A. Banerjee, P. Basu, P. Dasgupta, P. P. Chakrabarti, C. Rama Mohan, L. Fix

18th International Conference on VLSI Design, Kolkata, India, 3/-2/5, 201-206, IEEE Computer Science Press, 2005.**Dictionary based code compression for variable length instruction encodings**by Dipankar Das, Rajeev Kumar, P. P. Chakrabarti

18th International Conference on VLSI Design, Kolkata, India, 3/1/2005, 545-550, IEEE Computer Science Press, 2005.**Multiobjective EA approach for improved quality of solutions for spanning tree problem**by Rajeev Kumar, P. K. Singh, P. P. Chakrabarti

International Conference on Evolutionary Multi-Criterion Optimization (EMO), Guanajuato, Mexico, 7/3/2005, 811-825, Springer (LNCS 3410), 2005.**Mixing global and local competition in genetic optimization based design space exploration of analog circuits**by Somani, P. P. Chakrabarti, A. Patra

ACM/IEEE Design Automation and Test in Europe (DATE), Munich, Germany, 7/3/2005, 1064-1069, ACM/IEEE, 2005.**A hierarchical cost tree mutation approach to optimization of analog circuits**by Somani, P. P. Chakrabarti, A. Patra

18th International Conference on VLSI Design, Kolkata, India, 3/1/2005, 535-538, IEEE Computer Science Press, 2005.**A verification system for transient response of analog circuits using model checking**by Tathagato Rai Dastidar, P. P. Chakrabarti

18th International Conference on VLSI Design, Kolkata, India, 3/1/2005, 195-200, IEEE Computer Science Press, 2005.**Boundary Fair Round Robin: A Fast Fair Scheduler**by Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar

VDAT 2005, Bangalore, India, 11/8/2005, 81-91, Elite Publishing, 2005.**An optimal algorithm for register renaming: a post compiling technique**by Sanjay Chatterjee, P. P. Chakrabarti, Rajeev Kumar

VDAT 2005, Bangalore, India, 11/8/0, 102-110, Elite Publishing, 2005.**Test plan coverage by formal property verification**by P. Basu, Sayantan Das, A. Banerjee, P. Dasgupta, P. P. Chakrabarti

VDAT 2005, Bangalore, India, 11/8/2005, 118-196, Elite Publishing, 2005.**Bounded model checking for Open-LTL**by Suchismita Roy, P. Dasgupta, P. P. Chakrabarti, Bounded model checking for Open-LTL

VDAT 2005, Bangalore, India, 11/8/2005, 297-303, Elite Publishing, 2005.**Syntax-driven approximate coverage analysis for an assertion suite against a high-leve formal model**by Sayantan Das, P. Basu, P. Dasgupta, P. P. Chakrabarti

VDAT 2005, Bangalore, India, 11/8/2005, 304-314, Elite Publishing, 2005.**SAT based solutions for Consistency Problems in Formal Property Specifications for Open Systems**by Roy, S., Das, S., Basu, P., Dasgupta, P., Chakrabarti, P.P.

ICCAD, 2005.**An adaptive framework for solving mulitple hard problems under time constraints**by Sandip Aine, Rajeev Kumar, and PP Chakrabarti

Int. Conf. Computational Intelligence and Security (CIS-05), Xi'an, China. LNCS, Springer, December 2005.**Adaptive control of anytime algorithm parameters**by Sandip Aine, Rajeev Kumar, and PP Chakrabarti

2nd Indian Int. Conf. Artificial Intelligence (IICAI-05), Pune, pp. 72 - 87, December 2005.**A method-based whole-program watermarking scheme for Java class files**by Anshuman Mishra, Rajeev Kumar, and PP Chakrabarti

12th Int. Conf. High Performance Computing Conference (HiPC), Goa, December 2005.**Best Poster Award****Solving hard real-world problems using multiobjective evolutionary algorithm**by PK Singh, Rajeev Kumar, and PP Chakrabarti

Int. Conf. Challenges and Opportunities in IT Industry, Ludhiana, Nov. 2005.**Adaptive parameter control of evolutionary algorithms under time constraints**by Sandip Aine, Rajeev Kumar, and PP Chakrabarti

Applications of Soft Computing: Recent Trends, ISBN 3-540-291-23-7. Springer, May 2006.**Improving the performance of CAD optimization algorithms using on-line meta-level control**by Sandip Aine, PP Chakrabarti, and Rajeev Kumar

19th Int. Conf. VLSI Design/ 5th Int. Conf. Embedded System, Hyderabad, pp. 683 - 688, IEEE CS Press, January 2006.**Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-time Embedded Systems**by Arnab Sarkar, P P Chakrabarti, Rajeev Kumar

19th International Conference on VLSI Design, Hyderabad, January, 2006.**Instruction-Set-Extension Exploration Using Decomposable Heuristic Search**by Samik Das, P. P. Chakabarti, Pallab Dasgupta

19th International Conference on VLSI Design, Hyderabad, January, 2006.**Synthesis of system verilog assertions**by Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti

DATE Designers' Forum 70-75, Munich 2006.**What lies between Design Intent Coverage and Model Checking?**by Das, S., Basu, P., Dasgupta, P., Chakrabarti, P.P.

DATE, Munich, pp 1217-1222. 2006.**Discovering the Input Assumptions in Specification Refinement Coverage**by Basu, P., Das, S., Dasgupta, P., Chakrabarti, P.P.

ASPDAC, Japan,. pp 13-18, 2006.**Design Intent Specification and Verification: New Challenges to Intelligent Automation**by P. P. Chakrabarti

ICIT 2006, Mumbai, 2006.**Keynote Lecture****Formal Verification of Power Scheduling Policies for Battery Powered Mobile Systems**by Sayak Ray, P.Dasgupta, P.P.Chakrabarti

IEEE Indicon, New Delhi, 2006.**Property Driven Test Generation in absence of Direct Interface**by B.Pal, P.Dasgupta, P.P.Chakrabarti

IEEE INDICON, New Delhi, 2006.**Detecting Faults at the time they occur**by A.Kumar, S.Das, P.Dasgupta, P.P.Chakrabarti

VDAT 2006, Goa, 2006.**Automatic Test Generation for Temporal Coverage Points using a Stochastic Tree Model**by A. Nandi, B.Pal, P.Dasgupta, P.P.Chakrabarti

VDAT 2006, Goa, 2006.**Exact method for estimating expected settling power in Sequential Circuits**by D.Chakraborty, P.P.Chakrabarti, P.Dasgupta

VDAT 2006, Goa, 2006.**A Framework for Estimating Peak Power in Gate-Level Circuits**by Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta

PATMOS pp 573-582, France 2006.**Improving Standard Cell Placement Through Adaptive Parameter Control**by Sandip Aine, Rajeev Kumar, P.P. Chakrabarti

IEEE Int. Conference on Industrial Technology (ICIT 2006), Mumbai 2006.**Formal Methods for Checking Realizability of Coalitions in 3-party systems**by Banerjee, A., Dasgupta, P., Chakrabarti, P.P.

MEMOCODE 2006.**SystemC Modeling and Validation of A Pipelined RISC Processor Based System**by Rajeev Kumar, Rahul Chaudhry, Dipankar Das, Vibha Rathi, S.K. Panda, and P.P. Chakrabarti

Forum of Specification & Design Languages (FDL-06), Darmstadt, Germany, pp. 189 - 196, September 2006.**Timing verification of UML activity diagram based code block level models for real-time multiprocessor system-on-chip Applications**by Dipankar Das, Rajeev Kumar, and PP Chakrabarti

13th Asia Pacific Software Engineering Conference (APSEC06), Bangalore, pp. 199 - 206, December 2006. IEEE CS Press.**Bounded Delay Timing Analysis Using Boolean Satisfiability**by Roy, Suchismita.; Chakrabarti, P.P.; Dasgupta, P.

20th Int. Conference on VLSI Design & 6th Int. Conf on Embedded Systems, pp 295 -302, Bangalore 2007.**Simulation Based Verification using Temporally Attributed Boolean Logic**by Panda, S.K.; Roy, A.; Chakrabarti, P.P.; Kumar, R.

20th Int. Conference on VLSI Design & 6th Int. Conf on Embedded Systems, pp 57 -62, Bangalore 2007.**Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for Multiprocessors**by Choudhury, P.; Chakrabarti, P.P.; Kumar, R.

20th Int. Conference on VLSI Design & 6th Int. Conf on Embedded Systems, pp 89 -94, Bangalore 2007.**A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis**by Ray, Sayak .; Dasgupta, P.; Chakrabarti, P.P.

20th Int. Conference on VLSI Design & 6th Int. Conf on Embedded Systems, pp 95 -102, Bangalore 2007.**AWA* - A Window Constrained Anytime Heuristic Search Algorithm**by Sandip Aine, PP Chakrabarti, and Rajeev Kumar

12th Int. Joint Conference on Artificial Intelligence (IJCAI 07), pp 2250 - 2255, Hyderabad, 2007.**Realizability of Auxiliary State Machines + GR (1) LTL**by Banerjee, A., Dasgupta, P., Chakrabarti, P.P.

VDAT 2007.**Can Semi-Formal be made more formal?**by Banerjee, A., Dasgupta, P., Chakrabarti, P.P.

GM ISL Symposium, Jan 2007.**Timing Analysis of Sequential Circuits Using Symbolic Event Propagation**by Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta

ICCTA 2007: 151-157, Kolkata India 2007.**Scenario Driven Test Case Generation for Functional Verification of Pipelined Processors**by S. K. Panda, Venu Gopal Kasturi and Prof. P. P. Chakrabarti

11th IEEE VDAT2007 VLSI Design and Test Symposium, Kolkata, August 2007.**A Dynamic Assertion-based Verification Platform for UML Statecharts over Rhapsody**by Banerjee, A., Ray, S., Dasgupta, P., Chakrabarti P. P. Ramesh S. and Ganesan, P.V.V.

IEEE TENCON 2008.**Cohesive Coverage Management for Simulation and Formal Property Verification**by Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan

ISVLSI 2008, , 251-256, 2008.**A Dynamic Assertion-Based Verification Platform for Validation of UML Designs**by Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh, P. Vignesh V. Ganesan

ATVA 2008, , 222-227, 2008.**Quantified UML Collaboration Diagrams**by Worah, P., Banerjee, A., Chakrabarti, P.P., Dasgupta, P.

VDAT, 2008.**Approaches to Design Intent Verification**by Chakrabarti, P. P.

ICIIS 2008, Kharagpur 2008.**High-Level Design Intent Specification and Verification in Electronic Design Automation**by Chakrabarti, P. P.

Indo-Brazil Workshop Joint Workshop on Computational Techniques, Rio de Janeiro, 2008.**A priori Overload Detection and Avoidance in RT Fair Scheduled Systems**by Shaunak Chatterjee, Arnab Sarkar, P. P. Chakrabarti

10th High Performance Computing ASIA Conference HPC ASIA 2009, Kaohsiung, Taiwan, 93-100, IEEE. 2009.**Inline Assertions -- Embedding Formal Properties in a Test Bench**by Hazra, A., Ghosh, P., Dasgupta, P., Chakrabarti, P. P

22nd Int Conf on VLSI Design, New Delhi, 71- 76, IEEE, 2009.**Contract Search: An Adaptive Heuristic Search Strategy under Node Expansion Constraints**by Aine, S, Chakrabarti, P. P, Kumar Rajeev

SoCS 09, AAAI Inc, USA, 2009.**New Approaches to Design and Control of Time Limited Search Algorithms**by Chakrabarti, P.P., Aine S

PReMI 2009, New Delhi, Springer(2009).**Invited Paper****ERfair Scheduler with Processor Shutdown**by A. Sarkar, S. Swarup, S. Ghose and P. P. Chakrabarti

16th Annual International Conference on High Performance Computing (HiPC),Cochin,ACM, IEEE(2009)**Incremental Verification Techniques for an Updated Architectural Specification**by Srobona Mitra, Priyankar Ghosh, Pallab Dasgupta, P.P.Chakrabarti

IEEE India Conference (INDICON) 2009,Gandhinagar,(2009)**Accelerating Synchronous Sequential Circuits Using an Adaptive Clock**by Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta

23rd International Conference on VLSI Design (VLSID), Jan, 2010.,Bangalore,IEEE(2010)**Safe-ERfair - A priori Overload Handling in Fair Scheduled Embedded Systems**by A. Sarkar, R. Nanda, S. Ghose and P. P. Chakrabarti

23rd International Conference on VLSI Design (VLSID),Bangalore,IEEE(2010)**Coverage Management with Inline Assertions and Formal Test Points**by Hazra A., Ghosh P., Dasgupta P., Chakrabarti P. P

23rd International Conference on VLSI Design (VLSID),Bangalore,IEEE(2010)**Best Student Paper****An Analysis of Breadth-First Beam Search using Uniform Cost Trees**by Sandip Aine and PP Chakrabarti

Symposium of Artificial Intelligence and Mathematics (ISAIM),Florida, USA,(2010)**Contract Search: Heuristic Search under Node Expansion Constraints**by Sandip Aine, P. P. Chakrabarti, Rajeev Kumar

ECAI 2010: 733-738, 2010.**Layout Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip**by Sudip Roy, Bhargab B Bhattacharyya, P P Chakrabarti, Krishnendu Chakrabarty

24th International Conference on VLSI Design (VLSID), 2011 Chennai, pp 171- 176.**Robust Embedded Software Design through early analysis of Quality Faults**by Dipankar Das, Purnendu Sinha, P P Chakrabarti

ISEC 2011, pp 31-40.**A Framework For Early Stage Quality-Fault Tolerance Analysis Of Embedded Control Systems**by S G Vadlamudi, P. P. Chakrabarti, Dipankar Das, Purnendu Sinha

DSN 2011, Hong Kong, pp 315-322.**Design Intent Verification of Automotive Architectures and Applications**by P. P. Chakrabarti

26th National Convention of Computer Engineers, Guwahati, Feb 4, 2012.**M S Ramanujam Memorial Lecture****Panel Discussion: SoC Realization - A Bridge to New Horizons or a Bridge to Nowhere?**by Sathyam K. Pattanam, P. P. Chakrabarti, Mahesh Mahendale, Srikanth Jadcherla, Seer Akademi, Vikas Gautham, Raju Bala Showry Pudota

VLSI Design 2012: 38**Execution ordering in AND/OR Graphs with Failure Probabilities**by Priyankar Ghosh, P. P. Chakrabarti, Pallab Dasgupta

5th Annual Symposium on Combinatorial Search, SOCS 2012, Canada**Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips**by Sudip Roy, P. P. Chakrabarti, Bhargab B. Bhattacharya

ISVLSI 2012: 7-8, 2012**Anytime Algorithms for Bi-Objective Heuristic Search**by Priyankar Ghosh, P. P. Chakrabarti, Pallab Dasgupta

25th Australasian Joint Conference on Artificial Intelligence 2012, pp.230-241, Sydney, Australia.**Anytime Column Search**by S G Vadlamudi, Piyush Gaurav, Sandip Aine, P. P. Chakrabarti

25th Australasian Joint Conference on Artificial Intelligence 2012, pp.254-265, Sydney, Australia.**Anytime Algorithms for Mining Groups with Maximum Coverage**by S. G. Vadlamudi, P. P. Chakrabarti, Sudeshna Sarkar

10th Australasian Data Mining Conference (AusDM), pp.209-220, 5-7 Dec. 2012, Sydney, Australia.**Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults**by Vishal Shrivastav, S. G. Vadlamudi, P. P. Chakrabarti, Dipankar Das, Purnendu Sinha

3rd International Symposium on Electronic System Design (ISED), pp.167-171, 19-22 Dec. 2012, Kolkata, India.**Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control Tasks**by Saptarshi Roy, Amit Patra, P. P. Chakrabarti, Purnendu Sinha and Dipankar Das

26th International Conference on VLSI Design (VLSID), pp.19-24, 2013 Pune, India.**Efficient mixture preparation on digital microfluidic biochips**by Srijan Kumar, Sudip Roy, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya, Krishnendu Chakrabarty

DDECS 2013: 205-210**Algorithms for Generating Ordered Solutions for Explicit AND/OR Structures : Extended Abstract**by Priyankar Ghosh, Amit Sharma, Partha Pratim Chakrabarti, Pallab Dasgupta

IJCAI 2013**A Mobility Simulation Framework Of Humans With Group Behavior Modeling**by Anshul Gupta, Aurosish Mishra, S. G. Vadlamudi, P. P. Chakrabarti, Sudeshna Sarkar, Tridib Mukherjee, Nathan Gnanasambandam

IEEE 13th International Conference on Data Mining (ICDM), pp.1067-1072, 7-10 Dec. 2013, Dallas, USA.**Anytime Contract Search**by Sunandita Patra, S. G. Vadlamudi, P. P. Chakrabarti

33rd BCS SGAI International Conference on Artificial Intelligence (AI), Springer, Research and Development in Intelligent Systems XXX, pp.139-155, 10-12 Dec. 2013, Cambridge, England.**Ordered Solution Generation for Implicit AND/OR Search Spaces**by Priyankar Ghosh, Partha Pratim Chakrabarti, Pallab Dasgupta

5th International Conference on Pattern Recognition and Machine Intelligence (PReMI), Springer, LNCS, vol.8251 (Pattern Recognition and Machine Intelligence), pp.581-586, 10-14 Dec. 2013, Kolkata, India.**Anytime Pack Heuristic Search**by S. G. Vadlamudi, Sandip Aine, P. P. Chakrabarti

5th International Conference on Pattern Recognition and Machine Intelligence (PReMI), Springer, LNCS, vol.8251 (Pattern Recognition and Machine Intelligence), pp.628-634, 10-14 Dec. 2013, Kolkata, India.

Some more recent articles available at DBLP.