data_path Project Status (11/01/2012 - 23:38:33) | |||
Project File: | kgprisc.xise | Parser Errors: | No Errors |
Module Name: | alu | Implementation State: | Placed and Routed |
Target Device: | xc3s400-5pq208 |
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Product Version: | ISE 12.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 312 | 3584 | 8% | |
Number of Slice Flip Flops | 32 | 7168 | 0% | |
Number of 4 input LUTs | 538 | 7168 | 7% | |
Number of bonded IOBs | 104 | 141 | 73% | |
Number of GCLKs | 1 | 8 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed 31. Oct 23:38:18 2012 | ||||
Translation Report | Out of Date | Wed 31. Oct 19:42:46 2012 | ||||
Map Report | Out of Date | Wed 31. Oct 19:42:50 2012 | ||||
Place and Route Report | Out of Date | Wed 31. Oct 19:42:57 2012 | ||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | Wed 31. Oct 19:43:00 2012 | ||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Thu 1. Nov 23:38:39 2012 | |
Post-Place and Route Simulation Model Report | Out of Date | Thu 1. Nov 23:38:28 2012 |