Single_Cycle Project Status | |||
Project File: | kgprisc.xise | Parser Errors: | No Errors |
Module Name: | Single_Cycle | Implementation State: | Placed and Routed |
Target Device: | xc3s400-5pq208 |
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No Errors |
Product Version: | ISE 12.4 |
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357 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Total Number Slice Registers | 16 | 7,168 | 1% | ||
Number used as Flip Flops | 3 | ||||
Number used as Latches | 13 | ||||
Number of 4 input LUTs | 66 | 7,168 | 1% | ||
Number of occupied Slices | 39 | 3,584 | 1% | ||
Number of Slices containing only related logic | 39 | 39 | 100% | ||
Number of Slices containing unrelated logic | 0 | 39 | 0% | ||
Total Number of 4 input LUTs | 67 | 7,168 | 1% | ||
Number used as logic | 66 | ||||
Number used as a route-thru | 1 | ||||
Number of bonded IOBs | 136 | 141 | 96% | ||
IOB Latches | 6 | ||||
Number of RAMB16s | 2 | 16 | 12% | ||
Number of BUFGMUXs | 1 | 8 | 12% | ||
Average Fanout of Non-Clock Nets | 3.01 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu 1. Nov 23:37:55 2012 | 0 | 292 Warnings (0 new) | 105 Infos (0 new) | |
Translation Report | Current | Thu 1. Nov 23:38:02 2012 | 0 | 32 Warnings (0 new) | 0 | |
Map Report | Current | Thu 1. Nov 23:38:07 2012 | 0 | 33 Warnings (0 new) | 4 Infos (0 new) | |
Place and Route Report | Current | Thu 1. Nov 23:38:19 2012 | 0 | 0 | 3 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Thu 1. Nov 23:38:22 2012 | 0 | 0 | 5 Infos (0 new) | |
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Thu 1. Nov 23:49:30 2012 | |
Post-Place and Route Simulation Model Report | Current | Thu 1. Nov 23:38:28 2012 |