data_path Project Status (11/01/2012 - 23:38:33)
Project File: kgprisc.xise Parser Errors: No Errors
Module Name: alu Implementation State: Placed and Routed
Target Device: xc3s400-5pq208
  • Errors:
 
Product Version:ISE 12.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 312 3584 8%
Number of Slice Flip Flops 32 7168 0%
Number of 4 input LUTs 538 7168 7%
Number of bonded IOBs 104 141 73%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed 31. Oct 23:38:18 2012   
Translation ReportOut of DateWed 31. Oct 19:42:46 2012   
Map ReportOut of DateWed 31. Oct 19:42:50 2012   
Place and Route ReportOut of DateWed 31. Oct 19:42:57 2012   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportOut of DateWed 31. Oct 19:43:00 2012   
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu 1. Nov 23:38:39 2012
Post-Place and Route Simulation Model ReportOut of DateThu 1. Nov 23:38:28 2012

Date Generated: 11/01/2012 - 23:41:26