Release 12.4 - xst M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Reading design: system_timer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "system_timer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "system_timer"
Output Format                      : NGC
Target Device                      : xc6slx150-3-fgg484

---- Source Options
Top Module Name                    : system_timer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"D:/abhishek_microblaze/timer_microblaze/system/hdl/system.v\" into library work
Parsing module <system>.
Parsing module <microblaze_0_wrapper>.
Parsing module <mb_plb_wrapper>.
Parsing module <ilmb_wrapper>.
Parsing module <dlmb_wrapper>.
Parsing module <dlmb_cntlr_wrapper>.
Parsing module <ilmb_cntlr_wrapper>.
Parsing module <lmb_bram_wrapper>.
Parsing module <xps_timer_0_wrapper>.
Parsing module <generic_gpio_wrapper>.
Parsing module <clock_generator_0_wrapper>.
Parsing module <mdm_0_wrapper>.
Parsing module <proc_sys_reset_0_wrapper>.
Analyzing Verilog file \"\abhishek_microblaze\timer_microblaze\system_timer.v\" into library work
Parsing module <system_timer>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <system_timer>.

Elaborating module <system>.
WARNING:HDLCompiler:1499 - "D:/abhishek_microblaze/timer_microblaze/system/hdl/system.v" Line 5: Empty module <system> remains a black box.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system_timer>.
    Related source file is "/abhishek_microblaze/timer_microblaze/system_timer.v".
    Set property "BOX_TYPE = user_black_box" for instance <instance_name>.
    Summary:
	no macro.
Unit <system_timer> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <system.ngc>.
Loading core <system> for timing and area information for instance <instance_name>.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <system_timer> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block system_timer, actual ratio is 0.
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit <mb_plb> is equivalent to the following 5 FFs/Latches : <mb_plb/GEN_MPLB_RST[0].I_MPLB_RST> <mb_plb/GEN_SPLB_RST[2].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[1].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1> in Unit <mb_plb> is equivalent to the following 2 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_2> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0> in Unit <mb_plb> is equivalent to the following 2 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_2> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[21].TCSR1_FF_I> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[21].TCSR0_FF_I> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2_1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_6> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_6_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit <mb_plb> is equivalent to the following 5 FFs/Latches : <mb_plb/GEN_MPLB_RST[0].I_MPLB_RST> <mb_plb/GEN_SPLB_RST[2].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[1].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1> in Unit <mb_plb> is equivalent to the following 2 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_2> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0> in Unit <mb_plb> is equivalent to the following 2 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_2> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[21].TCSR1_FF_I> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[21].TCSR0_FF_I> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2_1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_6> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_6_1> 

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : system_timer.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 2896
#      GND                         : 13
#      INV                         : 25
#      LUT1                        : 44
#      LUT2                        : 187
#      LUT3                        : 535
#      LUT4                        : 442
#      LUT5                        : 347
#      LUT6                        : 642
#      MULT_AND                    : 2
#      MUXCY                       : 136
#      MUXCY_L                     : 221
#      MUXF7                       : 117
#      VCC                         : 9
#      XORCY                       : 176
# FlipFlops/Latches                : 2067
#      FD                          : 226
#      FDC                         : 4
#      FDC_1                       : 5
#      FDCE                        : 31
#      FDE                         : 350
#      FDE_1                       : 8
#      FDP                         : 5
#      FDR                         : 540
#      FDRE                        : 845
#      FDRE_1                      : 1
#      FDS                         : 16
#      FDSE                        : 36
# RAMS                             : 48
#      RAM32M                      : 16
#      RAMB16BWER                  : 32
# Shift Registers                  : 115
#      SRL16                       : 3
#      SRL16E                      : 32
#      SRLC16E                     : 80
# Clock Buffers                    : 5
#      BUFG                        : 5
# IO Buffers                       : 3
#      IBUF                        : 2
#      IOBUF                       : 1
# DSPs                             : 3
#      DSP48A1                     : 3
# Others                           : 82
#      AND2B1L                     : 1
#      BSCAN_SPARTAN6              : 1
#      LUT6_2                      : 79
#      PLL_ADV                     : 1

Device utilization summary:
---------------------------

Selected Device : 6slx150fgg484-3 


Slice Logic Utilization: 
 Number of Slice Registers:            2067  out of  184304     1%  
 Number of Slice LUTs:                 2480  out of  92152     2%  
    Number used as Logic:              2301  out of  92152     2%  
    Number used as Memory:              179  out of  21680     0%  
       Number used as RAM:               64
       Number used as SRL:              115

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   3489
   Number with an unused Flip Flop:    1422  out of   3489    40%  
   Number with an unused LUT:          1009  out of   3489    28%  
   Number of fully used LUT-FF pairs:  1058  out of   3489    30%  
   Number of unique control sets:       125

IO Utilization: 
 Number of IOs:                           3
 Number of bonded IOBs:                   3  out of    338     0%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:               32  out of    268    11%  
    Number using Block RAM only:         32
 Number of BUFG/BUFGCTRLs:                5  out of     16    31%  
 Number of DSP48A1s:                      3  out of    180     1%  
 Number of PLL_ADVs:                      1  out of      6    16%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+---------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                         | Load  |
-----------------------------------+---------------------------------------------------------------+-------+
fpga_0_clk_1_sys_clk_pin           | clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst:CLKOUT0| 1989  |
instance_name/mdm_0/mdm_0/drck_i   | BUFG                                                          | 202   |
instance_name/mdm_0/mdm_0/update   | BUFG                                                          | 42    |
-----------------------------------+---------------------------------------------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 9.770ns (Maximum Frequency: 102.355MHz)
   Minimum input arrival time before clock: 7.508ns
   Maximum output required time after clock: 8.726ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'fpga_0_clk_1_sys_clk_pin'
  Clock period: 7.843ns (frequency: 127.506MHz)
  Total number of paths / destination ports: 215715 / 6241
-------------------------------------------------------------------------
Delay:               7.843ns (Levels of Logic = 0)
  Source:            instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op2_31 (FF)
  Destination:       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48A.Normal_in_fabric.DSP48A_I1 (DSP)
  Source Clock:      fpga_0_clk_1_sys_clk_pin rising
  Destination Clock: fpga_0_clk_1_sys_clk_pin rising

  Data Path: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op2_31 to instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48A.Normal_in_fabric.DSP48A_I1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            49   0.447   1.533  microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op2_31 (microblaze_0/Performance.Data_Flow_I/ex_op2<31>)
     DSP48A1:B0                5.863          microblaze_0/Performance.Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48A.Normal_in_fabric.DSP48A_I1
    ----------------------------------------
    Total                      7.843ns (6.310ns logic, 1.533ns route)
                                       (80.5% logic, 19.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'instance_name/mdm_0/mdm_0/drck_i'
  Clock period: 7.680ns (frequency: 130.203MHz)
  Total number of paths / destination ports: 299 / 247
-------------------------------------------------------------------------
Delay:               3.840ns (Levels of Logic = 3)
  Source:            instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE (FF)
  Destination:       instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_7 (FF)
  Source Clock:      instance_name/mdm_0/mdm_0/drck_i falling
  Destination Clock: instance_name/mdm_0/mdm_0/drck_i rising

  Data Path: instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE to instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE_1:C->Q           1   0.447   0.924  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/sync)
     LUT6:I1->O            9   0.203   0.829  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Mmux_shifting_Data11 (Dbg_Shift_7)
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     INV:I->O              8   0.206   0.802  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Shift_inv1_INV_0 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Shift_inv)
     FDR:R                     0.430          microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_7
    ----------------------------------------
    Total                      3.840ns (1.286ns logic, 2.554ns route)
                                       (33.5% logic, 66.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'instance_name/mdm_0/mdm_0/update'
  Clock period: 9.770ns (frequency: 102.355MHz)
  Total number of paths / destination ports: 334 / 52
-------------------------------------------------------------------------
Delay:               4.885ns (Levels of Logic = 4)
  Source:            instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
  Destination:       instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/single_Step_TClk (FF)
  Source Clock:      instance_name/mdm_0/mdm_0/update falling
  Destination Clock: instance_name/mdm_0/mdm_0/update rising

  Data Path: instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I to instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/single_Step_TClk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           14   0.447   1.062  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd)
     LUT2:I0->O            4   0.203   0.931  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Mmux_Dbg_Reg_En_I11 (Dbg_Reg_En_0<0>)
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     LUT4:I0->O            4   0.203   0.684  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Command_Reg_En31 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Command_Reg_En_bdd4)
     LUT5:I4->O            9   0.205   0.829  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Control_Reg_En1 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Control_Reg_En)
     FDCE:CE                   0.322          microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/single_Step_TClk
    ----------------------------------------
    Total                      4.885ns (1.380ns logic, 3.505ns route)
                                       (28.3% logic, 71.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'fpga_0_clk_1_sys_clk_pin'
  Total number of paths / destination ports: 34 / 34
-------------------------------------------------------------------------
Offset:              2.146ns (Levels of Logic = 3)
  Source:            fpga_0_rst_1_sys_rst_pin (PAD)
  Destination:       instance_name/proc_sys_reset_0/proc_sys_reset_0/EXT_LPF/exr_d1 (FF)
  Destination Clock: fpga_0_clk_1_sys_clk_pin rising

  Data Path: fpga_0_rst_1_sys_rst_pin to instance_name/proc_sys_reset_0/proc_sys_reset_0/EXT_LPF/exr_d1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.222   0.617  fpga_0_rst_1_sys_rst_pin_IBUF (fpga_0_rst_1_sys_rst_pin_IBUF)
     begin scope: 'instance_name'
     begin scope: 'proc_sys_reset_0'
     LUT2:I1->O            1   0.205   0.000  proc_sys_reset_0/EXT_LPF/External_System_Reset_MB_Debug_Sys_Rst_OR_8_o1 (proc_sys_reset_0/EXT_LPF/External_System_Reset_MB_Debug_Sys_Rst_OR_8_o)
     FD:D                      0.102          proc_sys_reset_0/EXT_LPF/exr_d1
    ----------------------------------------
    Total                      2.146ns (1.529ns logic, 0.617ns route)
                                       (71.2% logic, 28.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'instance_name/mdm_0/mdm_0/drck_i'
  Total number of paths / destination ports: 143 / 123
-------------------------------------------------------------------------
Offset:              3.548ns (Levels of Logic = 3)
  Source:            instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:SHIFT (PAD)
  Destination:       instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_7 (FF)
  Destination Clock: instance_name/mdm_0/mdm_0/drck_i rising

  Data Path: instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:SHIFT to instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN6:SHIFT    5   0.000   1.079  mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I (Ext_JTAG_SHIFT)
     LUT6:I0->O            9   0.203   0.829  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Mmux_shifting_Data11 (Dbg_Shift_7)
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     INV:I->O              8   0.206   0.802  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Shift_inv1_INV_0 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/Shift_inv)
     FDR:R                     0.430          microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_7
    ----------------------------------------
    Total                      3.548ns (0.839ns logic, 2.709ns route)
                                       (23.6% logic, 76.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'instance_name/mdm_0/mdm_0/update'
  Total number of paths / destination ports: 29 / 29
-------------------------------------------------------------------------
Offset:              7.508ns (Levels of Logic = 6)
  Source:            instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:SEL (PAD)
  Destination:       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
  Destination Clock: instance_name/mdm_0/mdm_0/update falling

  Data Path: instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:SEL to instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN6:SEL     8   0.000   1.147  mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I (mdm_0/sel)
     LUT5:I0->O            1   0.203   0.827  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/_n01201 (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/sel_n_delay<0>)
     LUT4:I0->O            1   0.203   0.827  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[0].LUT_Delay (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[0].local_sel_n)
     LUT4:I0->O            1   0.203   0.827  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[1].LUT_Delay (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[1].local_sel_n)
     LUT4:I0->O            1   0.203   0.827  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[2].LUT_Delay (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[2].local_sel_n)
     LUT4:I0->O            1   0.203   0.827  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[3].LUT_Delay (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[3].local_sel_n)
     LUT4:I0->O            1   0.203   0.579  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[4].LUT_Delay (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[4].local_sel_n)
     FDC_1:CLR                 0.430          mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
    ----------------------------------------
    Total                      7.508ns (1.648ns logic, 5.860ns route)
                                       (22.0% logic, 78.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fpga_0_clk_1_sys_clk_pin'
  Total number of paths / destination ports: 18 / 3
-------------------------------------------------------------------------
Offset:              4.595ns (Levels of Logic = 7)
  Source:            instance_name/dlmb_cntlr/dlmb_cntlr/Sl_Ready_i (FF)
  Destination:       instance_name/microblaze_0/microblaze_0/Performance.Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1:DI (PAD)
  Source Clock:      fpga_0_clk_1_sys_clk_pin rising

  Data Path: instance_name/dlmb_cntlr/dlmb_cntlr/Sl_Ready_i to instance_name/microblaze_0/microblaze_0/Performance.Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1:DI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.447   0.684  dlmb_cntlr/Sl_Ready_i (dlmb_cntlr/Sl_Ready_i)
     LUT2:I0->O            4   0.203   0.788  dlmb_cntlr/Sl_Ready1 (Sl_Ready)
     end scope: 'dlmb_cntlr'
     begin scope: 'dlmb'
     end scope: 'dlmb'
     begin scope: 'microblaze_0'
     LUT2:I0->O            1   0.203   0.000  microblaze_0/Performance.mem_databus_ready_sel_carry_or/Using_FPGA.A_N1 (microblaze_0/Performance.mem_databus_ready_sel_carry_or/Using_FPGA.A_N)
     MUXCY_L:S->LO         1   0.172   0.000  microblaze_0/Performance.mem_databus_ready_sel_carry_or/Using_FPGA.MUXCY_I (microblaze_0/Performance.mem_databus_ready)
     MUXCY_L:CI->LO        1   0.019   0.000  microblaze_0/Performance.Decode_I/mem_wait_on_ready_N_carry_or/Using_FPGA.MUXCY_I (microblaze_0/Performance.Decode_I/mem_wait_on_ready_N)
     MUXCY_L:CI->LO      232   0.019   2.061  microblaze_0/Performance.Decode_I/mem_PipeRun_carry_and/Using_FPGA.MUXCY_I (Trace_MEM_PipeRun)
    AND2B1L:DI                 0.000          microblaze_0/Performance.Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1
    ----------------------------------------
    Total                      4.595ns (1.063ns logic, 3.532ns route)
                                       (23.1% logic, 76.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'instance_name/mdm_0/mdm_0/update'
  Total number of paths / destination ports: 78 / 1
-------------------------------------------------------------------------
Offset:              8.726ns (Levels of Logic = 10)
  Source:            instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
  Destination:       instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:TDO (PAD)
  Source Clock:      instance_name/mdm_0/mdm_0/update falling

  Data Path: instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I to instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:TDO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           14   0.447   1.062  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (mdm_0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd)
     LUT2:I0->O            4   0.203   1.048  mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Mmux_Dbg_Reg_En_I51 (Dbg_Reg_En_0<4>)
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     LUT6:I0->O            1   0.203   0.944  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO1 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO)
     LUT6:I0->O            1   0.203   0.580  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO5 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO4)
     LUT3:I2->O            1   0.205   0.944  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO6 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO5)
     LUT6:I0->O            1   0.203   0.808  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO23 (DBG_TDO)
     end scope: 'microblaze_0'
     begin scope: 'mdm_0'
     LUT6:I3->O            1   0.205   0.580  mdm_0/MDM_Core_I1/Mmux_TDO_i12 (mdm_0/MDM_Core_I1/Mmux_TDO_i11)
     LUT5:I4->O            1   0.205   0.684  mdm_0/MDM_Core_I1/Mmux_TDO_i13 (mdm_0/MDM_Core_I1/Mmux_TDO_i12)
     LUT6:I4->O            0   0.203   0.000  mdm_0/MDM_Core_I1/Mmux_TDO_i16 (mdm_0/tdo)
    BSCAN_SPARTAN6:TDO         0.000          mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I
    ----------------------------------------
    Total                      8.726ns (2.077ns logic, 6.649ns route)
                                       (23.8% logic, 76.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'instance_name/mdm_0/mdm_0/drck_i'
  Total number of paths / destination ports: 183 / 1
-------------------------------------------------------------------------
Offset:              7.947ns (Levels of Logic = 8)
  Source:            instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_2 (FF)
  Destination:       instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:TDO (PAD)
  Source Clock:      instance_name/mdm_0/mdm_0/drck_i rising

  Data Path: instance_name/microblaze_0/microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_2 to instance_name/mdm_0/mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I:TDO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             25   0.447   1.557  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count_2 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/shift_count<2>)
     LUT6:I0->O            1   0.203   0.808  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO8 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO7)
     LUT6:I3->O            1   0.205   0.827  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO10 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO9)
     LUT6:I2->O            1   0.203   0.808  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO20 (microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO19)
     LUT6:I3->O            1   0.205   0.808  microblaze_0/Performance.Use_Debug_Logic.Debug_Perf/TDO23 (DBG_TDO)
     end scope: 'microblaze_0'
     begin scope: 'mdm_0'
     LUT6:I3->O            1   0.205   0.580  mdm_0/MDM_Core_I1/Mmux_TDO_i12 (mdm_0/MDM_Core_I1/Mmux_TDO_i11)
     LUT5:I4->O            1   0.205   0.684  mdm_0/MDM_Core_I1/Mmux_TDO_i13 (mdm_0/MDM_Core_I1/Mmux_TDO_i12)
     LUT6:I4->O            0   0.203   0.000  mdm_0/MDM_Core_I1/Mmux_TDO_i16 (mdm_0/tdo)
    BSCAN_SPARTAN6:TDO         0.000          mdm_0/Use_Spartan6.BSCAN_SPARTAN6_I
    ----------------------------------------
    Total                      7.947ns (1.876ns logic, 6.071ns route)
                                       (23.6% logic, 76.4% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock fpga_0_clk_1_sys_clk_pin
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
fpga_0_clk_1_sys_clk_pin        |    7.843|         |         |         |
instance_name/mdm_0/mdm_0/drck_i|    4.486|         |         |         |
instance_name/mdm_0/mdm_0/update|    3.711|    2.978|         |         |
--------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock instance_name/mdm_0/mdm_0/drck_i
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
fpga_0_clk_1_sys_clk_pin        |    3.048|         |         |         |
instance_name/mdm_0/mdm_0/drck_i|    2.375|    3.840|    3.249|         |
instance_name/mdm_0/mdm_0/update|         |    5.172|    2.756|         |
--------------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock instance_name/mdm_0/mdm_0/update
--------------------------------+---------+---------+---------+---------+
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------+---------+---------+---------+---------+
fpga_0_clk_1_sys_clk_pin        |    1.706|         |         |         |
instance_name/mdm_0/mdm_0/drck_i|    1.263|         |         |         |
instance_name/mdm_0/mdm_0/update|         |    4.885|    7.868|         |
--------------------------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 21.00 secs
Total CPU time to Xst completion: 20.08 secs
 
--> 

Total memory usage is 162272 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :   14 (   0 filtered)

