<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
					twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
							   NETDELAY | 
							   NETSKEW | 
							   PATH |
							   DEFPERIOD |
							   UNCONSTPATH |
							   DEFPATH | 
							   PATH2SETUP |
							   UNCONSTPATH2SETUP | 
							   PATHCLASS | 
							   PATHDELAY | 
							   PERIOD |
							   FREQUENCY |
							   PATHBLOCK |
							   OFFSET |
							   OFFSETIN |
							   OFFSETINCLOCK | 
							   UNCONSTOFFSETINCLOCK |
							   OFFSETINDELAY |
							   OFFSETINMOD |
							   OFFSETOUT |
							   OFFSETOUTCLOCK |
							   UNCONSTOFFSETOUTCLOCK | 
							   OFFSETOUTDELAY |
							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
					   twEndPtCnt?,
					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
						twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
					  fDCMJit CDATA #IMPLIED
					  fPhaseErr CDATA #IMPLIED
					  sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
					  best CDATA #IMPLIED requested CDATA #IMPLIED
					  errors CDATA #IMPLIED
					  score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.4 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.4\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml system_timer.twx system_timer.ncd -o system_timer.twr
system_timer.pcf

</twCmdLine><twDesign>system_timer.ncd</twDesign><twDesignPath>system_timer.ncd</twDesignPath><twPCF>system_timer.pcf</twPCF><twPcfPath>system_timer.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx150</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.15 2010-12-02</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="4" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 24 MHz HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>20.000</twMinPer></twConstHead><twPinLimitRpt anchorID="5"><twPinLimitBanner>Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 24 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="6" type="MAXPERIOD" name="Tpllper_CLKIN" slack="10.964" period="41.666" constraintValue="41.666" deviceLimit="52.630" freqLimit="19.001" physResource="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1" logResource="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1" locationPin="PLL_ADV_X0Y3.CLKIN2" clockNet="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst_ML_NEW_DIVCLK"/><twPinLimit anchorID="7" type="MAXPERIOD" name="Tpllper_CLKFB" slack="10.964" period="41.666" constraintValue="41.666" deviceLimit="52.630" freqLimit="19.001" physResource="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKFBOUT" logResource="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKFBOUT" locationPin="PLL_ADV_X0Y3.CLKFBOUT" clockNet="instance_name/clock_generator_0/clock_generator_0/SIG_PLL0_CLKFBOUT"/><twPinLimit anchorID="8" type="MINLOWPULSE" name="Tdcmpw_CLKIN_10_25" slack="21.666" period="41.666" constraintValue="20.833" deviceLimit="10.000" physResource="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1" logResource="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1" locationPin="PLL_ADV_X0Y3.CLKIN2" clockNet="instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst_ML_NEW_DIVCLK"/></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD         TIMEGRP         &quot;instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0&quot;         TS_sys_clk_pin HIGH 50%;</twConstName><twItemCnt>337209</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>10329</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>15.491</twMinPer></twConstHead><twPathRptBanner iPaths="229" iCriticalPaths="0" sType="EndPoint">Paths for end point instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAMB16_X1Y4.WEB2), 229 paths
</twPathRptBanner><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.175</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.543</twTotPathDel><twClkSkew dest = "0.937" src = "0.773">-0.164</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X106Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X106Y80.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;28&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y77.A4</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.700</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;28&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y77.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.395</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;25&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[28].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6</twBEL><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y78.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y78.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;21&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y79.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y79.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;17&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y80.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y80.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;13&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y81.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y81.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.272</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;9&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.398</twDelInfo><twComp>instance_name/dlmb_LMB_ABus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB2</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.571</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.862</twLogDel><twRouteDel>13.681</twRouteDel><twTotDel>15.543</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>12.0</twPctLog><twPctRoute>88.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.316</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.402</twTotPathDel><twClkSkew dest = "0.937" src = "0.773">-0.164</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X104Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X104Y80.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;27&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y77.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.540</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;27&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y77.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.375</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;25&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[27].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6</twBEL><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y78.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y78.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;21&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y79.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y79.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;17&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y80.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y80.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;13&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y81.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y81.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.272</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;9&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.398</twDelInfo><twComp>instance_name/dlmb_LMB_ABus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB2</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.571</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.881</twLogDel><twRouteDel>13.521</twRouteDel><twTotDel>15.402</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>12.2</twPctLog><twPctRoute>87.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.385</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.389</twTotPathDel><twClkSkew dest = "0.937" src = "0.717">-0.220</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X102Y78.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X102Y78.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;30&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y76.B2</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">2.401</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;30&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X78Y76.BMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.251</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;2&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mxor_ex_unaligned_Addr_2LSb&lt;0&gt;_xo&lt;0&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y76.D2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.658</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.ex_addr_low_bits&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X78Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;2&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mmux_ex_DataBus_Byte_Enable_i31</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.336</twDelInfo><twComp>instance_name/dlmb_LMB_BE&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB2</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.571</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.423</twLogDel><twRouteDel>13.966</twRouteDel><twTotDel>15.389</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>9.2</twPctLog><twPctRoute>90.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="229" iCriticalPaths="0" sType="EndPoint">Paths for end point instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAMB16_X1Y4.WEB3), 229 paths
</twPathRptBanner><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.205</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.513</twTotPathDel><twClkSkew dest = "0.937" src = "0.773">-0.164</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X106Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X106Y80.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;28&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y77.A4</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.700</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;28&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y77.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.395</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;25&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[28].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6</twBEL><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y78.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y78.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;21&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y79.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y79.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;17&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y80.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y80.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;13&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y81.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y81.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.272</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;9&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.398</twDelInfo><twComp>instance_name/dlmb_LMB_ABus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB3</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.541</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.862</twLogDel><twRouteDel>13.651</twRouteDel><twTotDel>15.513</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>12.0</twPctLog><twPctRoute>88.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.346</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.372</twTotPathDel><twClkSkew dest = "0.937" src = "0.773">-0.164</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X104Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X104Y80.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;27&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y77.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.540</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;27&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y77.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.375</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;25&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[27].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6</twBEL><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y78.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y78.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;21&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y79.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y79.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;17&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y80.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y80.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;13&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y81.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y81.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.272</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;9&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.398</twDelInfo><twComp>instance_name/dlmb_LMB_ABus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB3</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.541</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.881</twLogDel><twRouteDel>13.491</twRouteDel><twTotDel>15.372</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>12.2</twPctLog><twPctRoute>87.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.415</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.359</twTotPathDel><twClkSkew dest = "0.937" src = "0.717">-0.220</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X102Y78.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X102Y78.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;30&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y76.B2</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">2.401</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;30&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X78Y76.BMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.251</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;2&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mxor_ex_unaligned_Addr_2LSb&lt;0&gt;_xo&lt;0&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y76.D2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.658</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.ex_addr_low_bits&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X78Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;2&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mmux_ex_DataBus_Byte_Enable_i31</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.336</twDelInfo><twComp>instance_name/dlmb_LMB_BE&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB3</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.541</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.300</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.423</twLogDel><twRouteDel>13.936</twRouteDel><twTotDel>15.359</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>9.3</twPctLog><twPctRoute>90.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="229" iCriticalPaths="0" sType="EndPoint">Paths for end point instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAMB16_X1Y4.WEB0), 229 paths
</twPathRptBanner><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.225</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.493</twTotPathDel><twClkSkew dest = "0.937" src = "0.773">-0.164</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X106Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X106Y80.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;28&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y77.A4</twSite><twDelType>net</twDelType><twFanCnt>11</twFanCnt><twDelInfo twEdge="twRising">1.700</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;28&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y77.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.395</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;25&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[28].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6</twBEL><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y78.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y78.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;21&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y79.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y79.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;17&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y80.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y80.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;13&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y81.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y81.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.272</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;9&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.398</twDelInfo><twComp>instance_name/dlmb_LMB_ABus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB0</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.571</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.250</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.812</twLogDel><twRouteDel>13.681</twRouteDel><twTotDel>15.493</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>11.7</twPctLog><twPctRoute>88.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.366</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.352</twTotPathDel><twClkSkew dest = "0.937" src = "0.773">-0.164</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>6</twLogLvls><twSrcSite>SLICE_X104Y80.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X104Y80.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.447</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;27&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y77.B1</twSite><twDelType>net</twDelType><twFanCnt>10</twFanCnt><twDelInfo twEdge="twRising">1.540</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;27&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y77.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.375</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;25&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[27].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6</twBEL><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y78.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y78.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;21&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y79.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y79.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;17&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y80.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y80.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.076</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;13&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X92Y81.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O</twComp></twPathDel><twPathDel><twSite>SLICE_X92Y81.DMUX</twSite><twDelType>Tcind</twDelType><twDelInfo twEdge="twRising">0.272</twDelInfo><twComp>instance_name/mb_plb_M_ABus&lt;9&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D5</twSite><twDelType>net</twDelType><twFanCnt>5</twFanCnt><twDelInfo twEdge="twRising">1.398</twDelInfo><twComp>instance_name/dlmb_LMB_ABus&lt;9&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB0</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.571</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.250</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.831</twLogDel><twRouteDel>13.521</twRouteDel><twTotDel>15.352</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>11.9</twPctLog><twPctRoute>88.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="26"><twConstPath anchorID="27" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>26.435</twSlack><twSrc BELType="FF">instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twSrc><twDest BELType="RAM">instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twTotPathDel>15.339</twTotPathDel><twClkSkew dest = "0.937" src = "0.717">-0.220</twClkSkew><twDelConst>41.666</twDelConst><twClkUncert fSysJit="0.070" fDCMJit="0.211" fPhaseErr="0.000" sEqu="((TSJ^2 + DJ^2)^1/2) / 2 + PE">0.112</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twSrc><twDest BELType='RAM'>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X102Y78.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X102Y78.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.408</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1&lt;30&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y76.B2</twSite><twDelType>net</twDelType><twFanCnt>13</twFanCnt><twDelInfo twEdge="twRising">2.401</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i&lt;30&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X78Y76.BMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.251</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;2&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mxor_ex_unaligned_Addr_2LSb&lt;0&gt;_xo&lt;0&gt;1</twBEL></twPathDel><twPathDel><twSite>SLICE_X78Y76.D2</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.658</twDelInfo><twComp>instance_name/microblaze_0/microblaze_0/Performance.ex_addr_low_bits&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X78Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.205</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;2&gt;</twComp><twBEL>instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mmux_ex_DataBus_Byte_Enable_i31</twBEL></twPathDel><twPathDel><twSite>SLICE_X79Y76.D4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.336</twDelInfo><twComp>instance_name/dlmb_LMB_BE&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X79Y76.D</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>instance_name/mb_plb_M_BE&lt;3&gt;</twComp><twBEL>instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we&lt;2&gt;&lt;2&gt;1</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y4.WEB0</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">10.571</twDelInfo><twComp>instance_name/dlmb_port_BRAM_WEN&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y4.CLKB</twSite><twDelType>Trcck_WEB</twDelType><twDelInfo twEdge="twRising">0.250</twDelInfo><twComp>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twComp><twBEL>instance_name/lmb_bram/lmb_bram/ramb16bwer_21</twBEL></twPathDel><twLogDel>1.373</twLogDel><twRouteDel>13.966</twRouteDel><twTotDel>15.339</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>9.0</twPctLog><twPctRoute>91.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD
        TIMEGRP
        &quot;instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0&quot;
        TS_sys_clk_pin HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I (SLICE_X80Y90.CE), 1 path
</twPathRptBanner><twPathRpt anchorID="28"><twConstPath anchorID="29" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.223</twSlack><twSrc BELType="FF">instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twSrc><twDest BELType="FF">instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I</twDest><twTotPathDel>0.223</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twSrc><twDest BELType='FF'>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X81Y91.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X81Y91.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twComp><twBEL>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X80Y90.CE</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twFalling">0.133</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X80Y90.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.108</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr&lt;3&gt;</twComp><twBEL>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I</twBEL></twPathDel><twLogDel>0.090</twLogDel><twRouteDel>0.133</twRouteDel><twTotDel>0.223</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>40.4</twPctLog><twPctRoute>59.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I (SLICE_X80Y90.CE), 1 path
</twPathRptBanner><twPathRpt anchorID="30"><twConstPath anchorID="31" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.227</twSlack><twSrc BELType="FF">instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twSrc><twDest BELType="FF">instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I</twDest><twTotPathDel>0.227</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twSrc><twDest BELType='FF'>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X81Y91.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X81Y91.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twComp><twBEL>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X80Y90.CE</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twFalling">0.133</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X80Y90.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.104</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr&lt;3&gt;</twComp><twBEL>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I</twBEL></twPathDel><twLogDel>0.094</twLogDel><twRouteDel>0.133</twRouteDel><twTotDel>0.227</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>41.4</twPctLog><twPctRoute>58.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I (SLICE_X80Y90.CE), 1 path
</twPathRptBanner><twPathRpt anchorID="32"><twConstPath anchorID="33" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.229</twSlack><twSrc BELType="FF">instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twSrc><twDest BELType="FF">instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I</twDest><twTotPathDel>0.229</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twSrc><twDest BELType='FF'>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X81Y91.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">instance_name/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X81Y91.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twComp><twBEL>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twBEL></twPathDel><twPathDel><twSite>SLICE_X80Y90.CE</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twFalling">0.133</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X80Y90.CLK</twSite><twDelType>Tckce</twDelType><twDelInfo twEdge="twFalling">-0.102</twDelInfo><twComp>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr&lt;3&gt;</twComp><twBEL>instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I</twBEL></twPathDel><twLogDel>0.096</twLogDel><twRouteDel>0.133</twRouteDel><twTotDel>0.229</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="41.666">instance_name/clk_50_0000MHz</twDestClk><twPctLog>41.9</twPctLog><twPctRoute>58.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="34"><twPinLimitBanner>Component Switching Limit Checks: TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD
        TIMEGRP
        &quot;instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0&quot;
        TS_sys_clk_pin HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="35" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="38.542" period="41.666" constraintValue="41.666" deviceLimit="3.124" freqLimit="320.102" physResource="instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKA" logResource="instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKA" locationPin="RAMB16_X3Y18.CLKA" clockNet="instance_name/clk_50_0000MHz"/><twPinLimit anchorID="36" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="38.542" period="41.666" constraintValue="41.666" deviceLimit="3.124" freqLimit="320.102" physResource="instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKB" logResource="instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKB" locationPin="RAMB16_X3Y18.CLKB" clockNet="instance_name/clk_50_0000MHz"/><twPinLimit anchorID="37" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="38.542" period="41.666" constraintValue="41.666" deviceLimit="3.124" freqLimit="320.102" physResource="instance_name/lmb_bram/lmb_bram/ramb16bwer_11/CLKA" logResource="instance_name/lmb_bram/lmb_bram/ramb16bwer_11/CLKA" locationPin="RAMB16_X4Y22.CLKA" clockNet="instance_name/clk_50_0000MHz"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="38"><twConstRollup name="TS_sys_clk_pin" fullName="TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 24 MHz HIGH 50%;" type="origin" depth="0" requirement="41.667" prefType="period" actual="20.000" actualRollup="15.491" errors="0" errorRollup="0" items="0" itemsRollup="337209"/><twConstRollup name="TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" fullName="TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD         TIMEGRP         &quot;instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0&quot;         TS_sys_clk_pin HIGH 50%;" type="child" depth="1" requirement="41.667" prefType="period" actual="15.491" actualRollup="N/A" errors="0" errorRollup="0" items="337209" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="39">0</twUnmetConstCnt><twDataSheet anchorID="40" twNameLen="24"><twClk2SUList anchorID="41" twDestWidth="24"><twDest>fpga_0_clk_1_sys_clk_pin</twDest><twClk2SU><twSrc>fpga_0_clk_1_sys_clk_pin</twSrc><twRiseRise>15.491</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="42"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>337209</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>11547</twConnCnt></twConstCov><twStats anchorID="43"><twMinPer>20.000</twMinPer><twFootnote number="1" /><twMaxFreq>50.000</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Sun Jan 26 17:30:52 2014 </twTimestamp></twFoot><twClientInfo anchorID="44"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 285 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
