--------------------------------------------------------------------------------
Release 12.4 Trace  (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

C:\Xilinx\12.4\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml system_timer.twx system_timer.ncd -o system_timer.twr
system_timer.pcf

Design file:              system_timer.ncd
Physical constraint file: system_timer.pcf
Device,package,speed:     xc6slx150,fgg484,C,-3 (PRODUCTION 1.15 2010-12-02)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 24 MHz HIGH 
50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is  20.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 24 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 10.964ns (max period limit - period)
  Period: 41.666ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKIN)
  Physical resource: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1
  Logical resource: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1
  Location pin: PLL_ADV_X0Y3.CLKIN2
  Clock network: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 10.964ns (max period limit - period)
  Period: 41.666ns
  Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKFB)
  Physical resource: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKFBOUT
  Logical resource: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKFBOUT
  Location pin: PLL_ADV_X0Y3.CLKFBOUT
  Clock network: instance_name/clock_generator_0/clock_generator_0/SIG_PLL0_CLKFBOUT
--------------------------------------------------------------------------------
Slack: 21.666ns (period - (min low pulse limit / (low pulse / period)))
  Period: 41.666ns
  Low pulse: 20.833ns
  Low pulse limit: 10.000ns (Tdcmpw_CLKIN_10_25)
  Physical resource: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1
  Logical resource: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst/CLKIN1
  Location pin: PLL_ADV_X0Y3.CLKIN2
  Clock network: instance_name/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst_ML_NEW_DIVCLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD  
       TIMEGRP         
"instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0"         
TS_sys_clk_pin HIGH 50%;

 337209 paths analyzed, 10329 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  15.491ns.
--------------------------------------------------------------------------------

Paths for end point instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAMB16_X1Y4.WEB2), 229 paths
--------------------------------------------------------------------------------
Slack (setup path):     26.175ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.543ns (Levels of Logic = 6)
  Clock Path Skew:      0.164ns (0.937 - 0.773)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X106Y80.CQ     Tcko                  0.408   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<28>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28
    SLICE_X92Y77.A4      net (fanout=11)       1.700   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<28>
    SLICE_X92Y77.COUT    Topcya                0.395   instance_name/mb_plb_M_ABus<25>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[28].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y78.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y78.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<21>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y79.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y79.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<17>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y80.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y80.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<13>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y81.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y81.DMUX    Tcind                 0.272   instance_name/mb_plb_M_ABus<9>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X79Y76.D5      net (fanout=5)        1.398   instance_name/dlmb_LMB_ABus<9>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB2     net (fanout=32)      10.571   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.300   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.543ns (1.862ns logic, 13.681ns route)
                                                       (12.0% logic, 88.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     26.316ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.402ns (Levels of Logic = 6)
  Clock Path Skew:      0.164ns (0.937 - 0.773)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y80.CQ     Tcko                  0.447   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<27>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27
    SLICE_X92Y77.B1      net (fanout=10)       1.540   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<27>
    SLICE_X92Y77.COUT    Topcyb                0.375   instance_name/mb_plb_M_ABus<25>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[27].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y78.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y78.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<21>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y79.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y79.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<17>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y80.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y80.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<13>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y81.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y81.DMUX    Tcind                 0.272   instance_name/mb_plb_M_ABus<9>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X79Y76.D5      net (fanout=5)        1.398   instance_name/dlmb_LMB_ABus<9>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB2     net (fanout=32)      10.571   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.300   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.402ns (1.881ns logic, 13.521ns route)
                                                       (12.2% logic, 87.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     26.385ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.389ns (Levels of Logic = 3)
  Clock Path Skew:      0.220ns (0.937 - 0.717)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X102Y78.CQ     Tcko                  0.408   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<30>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30
    SLICE_X78Y76.B2      net (fanout=13)       2.401   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<30>
    SLICE_X78Y76.BMUX    Tilo                  0.251   instance_name/mb_plb_M_BE<2>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mxor_ex_unaligned_Addr_2LSb<0>_xo<0>1
    SLICE_X78Y76.D2      net (fanout=4)        0.658   instance_name/microblaze_0/microblaze_0/Performance.ex_addr_low_bits<0>
    SLICE_X78Y76.D       Tilo                  0.205   instance_name/mb_plb_M_BE<2>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mmux_ex_DataBus_Byte_Enable_i31
    SLICE_X79Y76.D4      net (fanout=1)        0.336   instance_name/dlmb_LMB_BE<2>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB2     net (fanout=32)      10.571   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.300   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.389ns (1.423ns logic, 13.966ns route)
                                                       (9.2% logic, 90.8% route)

--------------------------------------------------------------------------------

Paths for end point instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAMB16_X1Y4.WEB3), 229 paths
--------------------------------------------------------------------------------
Slack (setup path):     26.205ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.513ns (Levels of Logic = 6)
  Clock Path Skew:      0.164ns (0.937 - 0.773)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X106Y80.CQ     Tcko                  0.408   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<28>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28
    SLICE_X92Y77.A4      net (fanout=11)       1.700   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<28>
    SLICE_X92Y77.COUT    Topcya                0.395   instance_name/mb_plb_M_ABus<25>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[28].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y78.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y78.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<21>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y79.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y79.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<17>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y80.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y80.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<13>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y81.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y81.DMUX    Tcind                 0.272   instance_name/mb_plb_M_ABus<9>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X79Y76.D5      net (fanout=5)        1.398   instance_name/dlmb_LMB_ABus<9>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB3     net (fanout=32)      10.541   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.300   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.513ns (1.862ns logic, 13.651ns route)
                                                       (12.0% logic, 88.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     26.346ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.372ns (Levels of Logic = 6)
  Clock Path Skew:      0.164ns (0.937 - 0.773)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y80.CQ     Tcko                  0.447   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<27>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27
    SLICE_X92Y77.B1      net (fanout=10)       1.540   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<27>
    SLICE_X92Y77.COUT    Topcyb                0.375   instance_name/mb_plb_M_ABus<25>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[27].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y78.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y78.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<21>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y79.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y79.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<17>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y80.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y80.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<13>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y81.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y81.DMUX    Tcind                 0.272   instance_name/mb_plb_M_ABus<9>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X79Y76.D5      net (fanout=5)        1.398   instance_name/dlmb_LMB_ABus<9>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB3     net (fanout=32)      10.541   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.300   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.372ns (1.881ns logic, 13.491ns route)
                                                       (12.2% logic, 87.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     26.415ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.359ns (Levels of Logic = 3)
  Clock Path Skew:      0.220ns (0.937 - 0.717)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X102Y78.CQ     Tcko                  0.408   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<30>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30
    SLICE_X78Y76.B2      net (fanout=13)       2.401   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<30>
    SLICE_X78Y76.BMUX    Tilo                  0.251   instance_name/mb_plb_M_BE<2>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mxor_ex_unaligned_Addr_2LSb<0>_xo<0>1
    SLICE_X78Y76.D2      net (fanout=4)        0.658   instance_name/microblaze_0/microblaze_0/Performance.ex_addr_low_bits<0>
    SLICE_X78Y76.D       Tilo                  0.205   instance_name/mb_plb_M_BE<2>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mmux_ex_DataBus_Byte_Enable_i31
    SLICE_X79Y76.D4      net (fanout=1)        0.336   instance_name/dlmb_LMB_BE<2>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB3     net (fanout=32)      10.541   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.300   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.359ns (1.423ns logic, 13.936ns route)
                                                       (9.3% logic, 90.7% route)

--------------------------------------------------------------------------------

Paths for end point instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAMB16_X1Y4.WEB0), 229 paths
--------------------------------------------------------------------------------
Slack (setup path):     26.225ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.493ns (Levels of Logic = 6)
  Clock Path Skew:      0.164ns (0.937 - 0.773)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X106Y80.CQ     Tcko                  0.408   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<28>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_28
    SLICE_X92Y77.A4      net (fanout=11)       1.700   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<28>
    SLICE_X92Y77.COUT    Topcya                0.395   instance_name/mb_plb_M_ABus<25>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[28].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y78.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y78.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<21>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y79.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y79.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<17>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y80.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y80.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<13>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y81.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y81.DMUX    Tcind                 0.272   instance_name/mb_plb_M_ABus<9>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X79Y76.D5      net (fanout=5)        1.398   instance_name/dlmb_LMB_ABus<9>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB0     net (fanout=32)      10.571   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.250   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.493ns (1.812ns logic, 13.681ns route)
                                                       (11.7% logic, 88.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     26.366ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.352ns (Levels of Logic = 6)
  Clock Path Skew:      0.164ns (0.937 - 0.773)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X104Y80.CQ     Tcko                  0.447   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<27>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_27
    SLICE_X92Y77.B1      net (fanout=10)       1.540   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<27>
    SLICE_X92Y77.COUT    Topcyb                0.375   instance_name/mb_plb_M_ABus<25>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[27].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.I_ALU_LUT_V5/LUT6
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y78.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[25].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y78.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<21>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y79.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[21].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y79.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<17>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y80.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[17].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y80.COUT    Tbyp                  0.076   instance_name/mb_plb_M_ABus<13>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X92Y81.CIN     net (fanout=1)        0.003   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[13].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I/O
    SLICE_X92Y81.DMUX    Tcind                 0.272   instance_name/mb_plb_M_ABus<9>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ALU_I/FPGA_Target.ALL_Bits[9].ALU_Bit_I1/Using_FPGA_LUT6.Not_Last_Bit.MUXCY_I
    SLICE_X79Y76.D5      net (fanout=5)        1.398   instance_name/dlmb_LMB_ABus<9>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB0     net (fanout=32)      10.571   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.250   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.352ns (1.831ns logic, 13.521ns route)
                                                       (11.9% logic, 88.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     26.435ns (requirement - (data path - clock path skew + uncertainty))
  Source:               instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30 (FF)
  Destination:          instance_name/lmb_bram/lmb_bram/ramb16bwer_21 (RAM)
  Requirement:          41.666ns
  Data Path Delay:      15.339ns (Levels of Logic = 3)
  Clock Path Skew:      0.220ns (0.937 - 0.717)
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.112ns

  Clock Uncertainty:          0.112ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.211ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30 to instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X102Y78.CQ     Tcko                  0.408   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Branch_CMP_Op1<30>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Operand_Select_I/EX_Op1_30
    SLICE_X78Y76.B2      net (fanout=13)       2.401   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/ex_op1_i<30>
    SLICE_X78Y76.BMUX    Tilo                  0.251   instance_name/mb_plb_M_BE<2>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mxor_ex_unaligned_Addr_2LSb<0>_xo<0>1
    SLICE_X78Y76.D2      net (fanout=4)        0.658   instance_name/microblaze_0/microblaze_0/Performance.ex_addr_low_bits<0>
    SLICE_X78Y76.D       Tilo                  0.205   instance_name/mb_plb_M_BE<2>
                                                       instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Byte_Doublet_Handle_gti_I/Mmux_ex_DataBus_Byte_Enable_i31
    SLICE_X79Y76.D4      net (fanout=1)        0.336   instance_name/dlmb_LMB_BE<2>
    SLICE_X79Y76.D       Tilo                  0.259   instance_name/mb_plb_M_BE<3>
                                                       instance_name/dlmb_cntlr/dlmb_cntlr/lmb_we<2><2>1
    RAMB16_X1Y4.WEB0     net (fanout=32)      10.571   instance_name/dlmb_port_BRAM_WEN<2>
    RAMB16_X1Y4.CLKB     Trcck_WEB             0.250   instance_name/lmb_bram/lmb_bram/ramb16bwer_21
                                                       instance_name/lmb_bram/lmb_bram/ramb16bwer_21
    -------------------------------------------------  ---------------------------
    Total                                     15.339ns (1.373ns logic, 13.966ns route)
                                                       (9.0% logic, 91.0% route)

--------------------------------------------------------------------------------

Hold Paths: TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD
        TIMEGRP
        "instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0"
        TS_sys_clk_pin HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I (SLICE_X80Y90.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.223ns (requirement - (clock path skew + uncertainty - data path))
  Source:               instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I (FF)
  Destination:          instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.223ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I to instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X81Y91.CQ      Tcko                  0.198   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
                                                       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
    SLICE_X80Y90.CE      net (fanout=4)        0.133   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
    SLICE_X80Y90.CLK     Tckce       (-Th)     0.108   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr<3>
                                                       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[3].FDRE_I
    -------------------------------------------------  ---------------------------
    Total                                      0.223ns (0.090ns logic, 0.133ns route)
                                                       (40.4% logic, 59.6% route)

--------------------------------------------------------------------------------

Paths for end point instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I (SLICE_X80Y90.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.227ns (requirement - (clock path skew + uncertainty - data path))
  Source:               instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I (FF)
  Destination:          instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.227ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I to instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X81Y91.CQ      Tcko                  0.198   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
                                                       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
    SLICE_X80Y90.CE      net (fanout=4)        0.133   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
    SLICE_X80Y90.CLK     Tckce       (-Th)     0.104   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr<3>
                                                       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[2].FDRE_I
    -------------------------------------------------  ---------------------------
    Total                                      0.227ns (0.094ns logic, 0.133ns route)
                                                       (41.4% logic, 58.6% route)

--------------------------------------------------------------------------------

Paths for end point instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I (SLICE_X80Y90.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.229ns (requirement - (clock path skew + uncertainty - data path))
  Source:               instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I (FF)
  Destination:          instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.229ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         instance_name/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    instance_name/clk_50_0000MHz rising at 41.666ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I to instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X81Y91.CQ      Tcko                  0.198   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
                                                       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
    SLICE_X80Y90.CE      net (fanout=4)        0.133   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I
    SLICE_X80Y90.CLK     Tckce       (-Th)     0.102   instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr<3>
                                                       instance_name/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/Addr_Counters[1].FDRE_I
    -------------------------------------------------  ---------------------------
    Total                                      0.229ns (0.096ns logic, 0.133ns route)
                                                       (41.9% logic, 58.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 = PERIOD
        TIMEGRP
        "instance_name_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0"
        TS_sys_clk_pin HIGH 50%;
--------------------------------------------------------------------------------
Slack: 38.542ns (period - min period limit)
  Period: 41.666ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKA
  Logical resource: instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKA
  Location pin: RAMB16_X3Y18.CLKA
  Clock network: instance_name/clk_50_0000MHz
--------------------------------------------------------------------------------
Slack: 38.542ns (period - min period limit)
  Period: 41.666ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
  Physical resource: instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKB
  Logical resource: instance_name/lmb_bram/lmb_bram/ramb16bwer_10/CLKB
  Location pin: RAMB16_X3Y18.CLKB
  Clock network: instance_name/clk_50_0000MHz
--------------------------------------------------------------------------------
Slack: 38.542ns (period - min period limit)
  Period: 41.666ns
  Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
  Physical resource: instance_name/lmb_bram/lmb_bram/ramb16bwer_11/CLKA
  Logical resource: instance_name/lmb_bram/lmb_bram/ramb16bwer_11/CLKA
  Location pin: RAMB16_X4Y22.CLKA
  Clock network: instance_name/clk_50_0000MHz
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     41.667ns|     20.000ns|     15.491ns|            0|            0|            0|       337209|
| TS_instance_name_clock_generat|     41.667ns|     15.491ns|          N/A|            0|            0|       337209|            0|
| or_0_clock_generator_0_SIG_PLL|             |             |             |             |             |             |             |
| 0_CLKOUT0                     |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock fpga_0_clk_1_sys_clk_pin
------------------------+---------+---------+---------+---------+
                        | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock            |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
------------------------+---------+---------+---------+---------+
fpga_0_clk_1_sys_clk_pin|   15.491|         |         |         |
------------------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 337209 paths, 0 nets, and 11547 connections

Design statistics:
   Minimum period:  20.000ns{1}   (Maximum frequency:  50.000MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Jan 26 17:30:52 2014 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 285 MB



