Release 12.4 - Bitgen M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '6slx150.nph' in environment
C:\Xilinx\12.4\ISE_DS\ISE\.
   "system_timer" is an NCD, version 3.2, device xc6slx150, package fgg484,
speed -3
Opened constraints file system_timer.pcf.

Sun Jan 26 17:30:59 2014

C:\Xilinx\12.4\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 system_timer.ncd 

Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 2**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| DonePin              | Pullup*              |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| Partial              | (Not Specified)*     |
+----------------------+----------------------+
| Encrypt              | No**                 |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| drive_awake          | No**                 |
+----------------------+----------------------+
| Reset_on_err         | No**                 |
+----------------------+----------------------+
| suspend_filter       | Yes*                 |
+----------------------+----------------------+
| en_sw_gsr            | No**                 |
+----------------------+----------------------+
| en_suspend           | No*                  |
+----------------------+----------------------+
| sw_clk               | Startupclk**         |
+----------------------+----------------------+
| sw_gwe_cycle         | 5**                  |
+----------------------+----------------------+
| sw_gts_cycle         | 4**                  |
+----------------------+----------------------+
| multipin_wakeup      | No**                 |
+----------------------+----------------------+
| wakeup_mask          | 0x00*                |
+----------------------+----------------------+
| ExtMasterCclk_en     | No**                 |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1*                   |
+----------------------+----------------------+
| glutmask             | Yes*                 |
+----------------------+----------------------+
| next_config_addr     | 0x00000000*          |
+----------------------+----------------------+
| next_config_new_mode | No*                  |
+----------------------+----------------------+
| next_config_boot_mode | 001*                 |
+----------------------+----------------------+
| next_config_register_write | Enable*              |
+----------------------+----------------------+
| golden_config_addr   | 0x00000000*          |
+----------------------+----------------------+
| failsafe_user        | 0x0000*              |
+----------------------+----------------------+
| TIMER_CFG            | 0xFFFF               |
+----------------------+----------------------+
| spi_buswidth         | 1**                  |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+
 *  Default setting.
 ** The specified setting matches the default setting.

There were 0 CONFIG constraint(s) processed from system_timer.pcf.


Running DRC.
WARNING:PhysDesignRules:367 - The signal <instance_name/dlmb_LMB_ABus<31>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <instance_name/dlmb_LMB_ABus<30>> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_Fil
   e_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The signal
   does not drive any load pins in the design.
DRC detected 0 errors and 18 warnings.  Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "system_timer.bit".
Bitstream generation is complete.
