Release 12.4 Map M.81d (nt)
Xilinx Map Application Log File for Design 'system_timer'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx150-fgg484-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o system_timer_map.ncd system_timer.ngd
system_timer.pcf 
Target Device  : xc6slx150
Target Package : fgg484
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.52.76.2 $
Mapped Date    : Sun Jan 26 17:28:17 2014

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 20 secs 
Total CPU  time at the beginning of Placer: 16 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:6c34a6e3) REAL time: 25 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:6c34a6e3) REAL time: 25 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:18268dcd) REAL time: 25 secs 

Phase 4.2  Initial Placement for Architecture Specific Features

Phase 4.2  Initial Placement for Architecture Specific Features (Checksum:55d13951) REAL time: 36 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:55d13951) REAL time: 36 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:55d13951) REAL time: 36 secs 

Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:55d13951) REAL time: 36 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:55d13951) REAL time: 36 secs 

Phase 9.8  Global Placement
..................................................................................................................................................
..............................................
Phase 9.8  Global Placement (Checksum:64375ab6) REAL time: 48 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:64375ab6) REAL time: 49 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:75783bec) REAL time: 53 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:75783bec) REAL time: 53 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:2b1fe64b) REAL time: 54 secs 

Total REAL time to Placer completion: 1 mins 8 secs 
Total CPU  time to Placer completion: 56 secs 
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <instance_name/dlmb_LMB_ABus<31>> is incomplete. The signal does not drive any
   load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <instance_name/dlmb_LMB_ABus<30>> is incomplete. The signal does not drive any
   load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RA
   MD_D1_O> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
   <instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_R
   AMD_D1_O> is incomplete. The signal does not drive any load pins in the design.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   18
Slice Logic Utilization:
  Number of Slice Registers:                 1,629 out of 184,304    1%
    Number used as Flip Flops:               1,624
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                5
  Number of Slice LUTs:                      1,945 out of  92,152    2%
    Number used as logic:                    1,770 out of  92,152    1%
      Number using O6 output only:           1,370
      Number using O5 output only:              90
      Number using O5 and O6:                  310
      Number used as ROM:                        0
    Number used as Memory:                     133 out of  21,680    1%
      Number used as Dual Port RAM:             64
        Number using O6 output only:             0
        Number using O5 output only:             0
        Number using O5 and O6:                 64
      Number used as Single Port RAM:            0
      Number used as Shift Register:            69
        Number using O6 output only:            24
        Number using O5 output only:             1
        Number using O5 and O6:                 44
    Number used exclusively as route-thrus:     42
      Number with same-slice register load:     36
      Number with same-slice carry load:         6
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   776 out of  23,038    3%
  Number of LUT Flip Flop pairs used:        2,320
    Number with an unused Flip Flop:           828 out of   2,320   35%
    Number with an unused LUT:                 375 out of   2,320   16%
    Number of fully used LUT-FF pairs:       1,117 out of   2,320   48%
    Number of unique control sets:             111
    Number of slice register sites lost
      to control set restrictions:             431 out of 184,304    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         3 out of     338    1%
    Number of LOCed IOBs:                        3 out of       3  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                        32 out of     268   11%
  Number of RAMB8BWERs:                          0 out of     536    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of      12    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     586    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     586    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     586    0%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            3 out of     180    1%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       4    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       6   16%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                4.20

Peak Memory Usage:  417 MB
Total REAL time to MAP completion:  1 mins 11 secs 
Total CPU time to MAP completion:   59 secs 

Mapping completed.
See MAP report file "system_timer_map.mrp" for details.
