Release 12.4 par M.81d (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

IIT-F3FD8D28C6B::  Sun Jan 26 17:29:30 2014

par -w -intstyle ise -ol high -mt off system_timer_map.ncd system_timer.ncd
system_timer.pcf 


Constraints file: system_timer.pcf.
Loading device for application Rf_Device from file '6slx150.nph' in environment C:\Xilinx\12.4\ISE_DS\ISE\.
   "system_timer" is an NCD, version 3.2, device xc6slx150, package fgg484, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.15 2010-12-02".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 1,629 out of 184,304    1%
    Number used as Flip Flops:               1,624
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                5
  Number of Slice LUTs:                      1,945 out of  92,152    2%
    Number used as logic:                    1,770 out of  92,152    1%
      Number using O6 output only:           1,370
      Number using O5 output only:              90
      Number using O5 and O6:                  310
      Number used as ROM:                        0
    Number used as Memory:                     133 out of  21,680    1%
      Number used as Dual Port RAM:             64
        Number using O6 output only:             0
        Number using O5 output only:             0
        Number using O5 and O6:                 64
      Number used as Single Port RAM:            0
      Number used as Shift Register:            69
        Number using O6 output only:            24
        Number using O5 output only:             1
        Number using O5 and O6:                 44
    Number used exclusively as route-thrus:     42
      Number with same-slice register load:     36
      Number with same-slice carry load:         6
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   776 out of  23,038    3%
  Number of LUT Flip Flop pairs used:        2,320
    Number with an unused Flip Flop:           828 out of   2,320   35%
    Number with an unused LUT:                 375 out of   2,320   16%
    Number of fully used LUT-FF pairs:       1,117 out of   2,320   48%
    Number of slice register sites lost
      to control set restrictions:               0 out of 184,304    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         3 out of     338    1%
    Number of LOCed IOBs:                        3 out of       3  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                        32 out of     268   11%
  Number of RAMB8BWERs:                          0 out of     536    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of      12    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     586    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     586    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     586    0%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            3 out of     180    1%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       4    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       6   16%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 13 secs 
Finished initial Timing Analysis.  REAL time: 13 secs 

WARNING:Par:288 - The signal instance_name/dlmb_LMB_ABus<31> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal instance_name/dlmb_LMB_ABus<30> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no load. 
   PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
   instance_name/microblaze_0/microblaze_0/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no load.
    PAR will not attempt to route this signal.
Starting Router


Phase  1  : 15848 unrouted;      REAL time: 16 secs 

Phase  2  : 11667 unrouted;      REAL time: 21 secs 

Phase  3  : 4764 unrouted;      REAL time: 38 secs 

Phase  4  : 4764 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 

Updating file: system_timer.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 57 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 57 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 57 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 57 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 57 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 59 secs 
Total REAL time to Router completion: 59 secs 
Total CPU time to Router completion: 51 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|instance_name/clk_50 |              |      |      |            |             |
|            _0000MHz | BUFGMUX_X3Y13| No   |  675 |  0.338     |  1.424      |
+---------------------+--------------+------+------+------------+-------------+
|instance_name/microb |              |      |      |            |             |
|laze_0_mdm_bus_Dbg_C |              |      |      |            |             |
|                  lk |  BUFGMUX_X2Y3| No   |   58 |  0.140     |  1.231      |
+---------------------+--------------+------+------+------------+-------------+
|instance_name/microb |              |      |      |            |             |
|laze_0_mdm_bus_Dbg_U |              |      |      |            |             |
|               pdate |         Local|      |   20 |  4.112     |  9.210      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |    21.666ns|    20.000ns|       0|           0
  pin" 24 MHz HIGH 50%                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_instance_name_clock_generator_0_clock_ | SETUP       |    26.175ns|    15.491ns|       0|           0
  generator_0_SIG_PLL0_CLKOUT0 = PERIOD     | HOLD        |     0.223ns|            |       0|           0
       TIMEGRP         "instance_name_clock |             |            |            |        |            
  _generator_0_clock_generator_0_SIG_PLL0_C |             |            |            |        |            
  LKOUT0"         TS_sys_clk_pin HIGH 50%   |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     41.667ns|     20.000ns|     15.491ns|            0|            0|            0|       337209|
| TS_instance_name_clock_generat|     41.667ns|     15.491ns|          N/A|            0|            0|       337209|            0|
| or_0_clock_generator_0_SIG_PLL|             |             |             |             |             |             |             |
| 0_CLKOUT0                     |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 18 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 1 mins 1 secs 
Total CPU time to PAR completion: 53 secs 

Peak Memory Usage:  411 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 20
Number of info messages: 0

Writing design to file system_timer.ncd



PAR done!
