Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.4 (WebPack) - M.81d Target Family: Virtex5
OS Platform: NT Target Device: xc5vlx50
Project ID (random number) ab83a2b9f7314bbba14f103c2b74081f.FE82185B5D4442ACA24B771B8AC44E0F.1 Target Package: ff324
Registration ID 0_0_0 Target Speed: -2
Date Generated 2014-05-31T21:42:25 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz CPU Speed 2926 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=1
  • 4-bit adder=1
Comparators=2
  • 12-bit comparator greatequal=2
Counters=8
  • 11-bit up counter=4
  • 11-bit updown counter=2
  • 16-bit up counter=1
  • 8-bit up counter=1
FSMs=1 Multiplexers=1
  • 128-bit 8-to-1 multiplexer=1
RAMs=2
  • 2048x8-bit dual-port block RAM=2
ROMs=1
  • 65536x8-bit ROM=1
Registers=1967
  • Flip-Flops=1967
Xors=2051
  • 1-bit xor2=1216
  • 1-bit xor3=512
  • 1-bit xor4=176
  • 1-bit xor5=48
  • 1-bit xor6=1
  • 128-bit xor2=3
  • 32-bit xor2=12
  • 8-bit xor2=59
  • 9-bit xor2=24
MiscellaneousStatistics
  • AGG_BONDED_IO=36
  • AGG_IO=36
  • AGG_LOCED_IO=36
  • AGG_SLICE=1381
  • NUM_BONDED_IOB=36
  • NUM_BSFULL=1194
  • NUM_BSLUTONLY=2683
  • NUM_BSREGONLY=374
  • NUM_BSUSED=4251
  • NUM_BUFG=2
  • NUM_LOCED_IOB=36
  • NUM_LOGIC_O5ANDO6=6
  • NUM_LOGIC_O5ONLY=58
  • NUM_LOGIC_O6ONLY=3807
  • NUM_LUT_RT_EXO6=6
  • NUM_LUT_RT_O5=3
  • NUM_LUT_RT_O6=56
  • NUM_OLOGIC=2
  • NUM_RAMB18X2=2
  • NUM_RAMB18X2_LOWER=2
  • NUM_SLICEL=1381
  • NUM_SLICE_CARRY4=24
  • NUM_SLICE_CONTROLSET=50
  • NUM_SLICE_CYINIT=3948
  • NUM_SLICE_F7MUX=291
  • NUM_SLICE_FF=1568
  • NUM_SLICE_UNUSEDCTRL=781
  • NUM_UNUSABLE_FF_BELS=48
NetStatistics
  • NumNets_Active=4241
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=947
  • NumNodesOfType_Active_BOUNCEIN=3040
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_CLKPIN=608
  • NumNodesOfType_Active_CNTRLPIN=971
  • NumNodesOfType_Active_DOUBLE=16705
  • NumNodesOfType_Active_GENERIC=2
  • NumNodesOfType_Active_GLOBAL=103
  • NumNodesOfType_Active_HLONG=25
  • NumNodesOfType_Active_INPUT=20216
  • NumNodesOfType_Active_IOBIN2OUT=12
  • NumNodesOfType_Active_IOBINPUT=22
  • NumNodesOfType_Active_IOBOUTPUT=34
  • NumNodesOfType_Active_OUTBOUND=4661
  • NumNodesOfType_Active_OUTPUT=4821
  • NumNodesOfType_Active_PADINPUT=22
  • NumNodesOfType_Active_PADOUTPUT=12
  • NumNodesOfType_Active_PENT=5180
  • NumNodesOfType_Active_PINBOUNCE=5642
  • NumNodesOfType_Active_PINFEED=21803
  • NumNodesOfType_Active_VLONG=362
  • NumNodesOfType_Vcc_INPUT=74
  • NumNodesOfType_Vcc_KVCCOUT=26
  • NumNodesOfType_Vcc_PINBOUNCE=5
  • NumNodesOfType_Vcc_PINFEED=74
SiteStatistics
  • BUFG-BUFGCTRL=2
  • IOB-IOBM=18
  • IOB-IOBS=18
  • RAMB18X2-RAMBFIFO36=2
  • SLICEL-SLICEM=400
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • IOB=36
  • IOB_IINV=1
  • IOB_INBUF=12
  • IOB_OUTBUF=24
  • IOB_PAD=36
  • OLOGIC=2
  • OLOGIC_O1USED=2
  • RAMB18X2=2
  • RAMB18X2_RAMB18X2_LOWER=2
  • SLICEL=1381
  • SLICEL_A5LUT=21
  • SLICEL_A6LUT=1156
  • SLICEL_AFF=496
  • SLICEL_B5LUT=18
  • SLICEL_B6LUT=1018
  • SLICEL_BFF=309
  • SLICEL_C5LUT=14
  • SLICEL_C6LUT=871
  • SLICEL_CARRY4=24
  • SLICEL_CFF=451
  • SLICEL_CYINITGND=6
  • SLICEL_D5LUT=14
  • SLICEL_D6LUT=830
  • SLICEL_DFF=312
  • SLICEL_F7AMUX=157
  • SLICEL_F7BMUX=134
 
Configuration Data
OLOGIC
  • D1=[D1:0] [D1_INV:2]
OLOGIC_O1USED
  • 0=[0:0] [0_INV:2]
RAMB18X2
  • CLKAL=[CLKAL_INV:0] [CLKAL:2]
  • CLKBL=[CLKBL:2] [CLKBL_INV:0]
  • ENAL=[ENAL_INV:0] [ENAL:2]
  • ENBL=[ENBL_INV:0] [ENBL:2]
  • REGCLKAL=[REGCLKAL:2] [REGCLKAL_INV:0]
  • REGCLKBL=[REGCLKBL_INV:0] [REGCLKBL:2]
  • SSRAL=[SSRAL:2] [SSRAL_INV:0]
  • SSRBL=[SSRBL:2] [SSRBL_INV:0]
RAMB18X2_RAMB18X2_LOWER
  • CLKAL=[CLKAL_INV:0] [CLKAL:2]
  • CLKBL=[CLKBL:2] [CLKBL_INV:0]
  • DOA_REG_L=[0:2]
  • DOB_REG_L=[0:2]
  • ENAL=[ENAL_INV:0] [ENAL:2]
  • ENBL=[ENBL_INV:0] [ENBL:2]
  • READ_WIDTH_A_L=[9:2]
  • READ_WIDTH_B_L=[9:2]
  • REGCLKAL=[REGCLKAL:2] [REGCLKAL_INV:0]
  • REGCLKBL=[REGCLKBL_INV:0] [REGCLKBL:2]
  • SAVEDATA_L=[FALSE:2]
  • SSRAL=[SSRAL:2] [SSRAL_INV:0]
  • SSRBL=[SSRBL:2] [SSRBL_INV:0]
  • WRITE_MODE_A_L=[WRITE_FIRST:2]
  • WRITE_MODE_B_L=[WRITE_FIRST:2]
  • WRITE_WIDTH_A_L=[9:2]
  • WRITE_WIDTH_B_L=[0:2]
SLICEL
  • CLK=[CLK:600] [CLK_INV:0]
SLICEL_AFF
  • AFFINIT=[INIT0:485] [INIT1:11]
  • AFFSR=[SRLOW:485] [SRHIGH:11]
  • CK=[CK:496] [CK_INV:0]
  • LATCH_OR_FF=[FF:496]
  • SYNC_ATTR=[ASYNC:295] [SYNC:201]
SLICEL_BFF
  • BFFINIT=[INIT0:309]
  • BFFSR=[SRLOW:309]
  • CK=[CK:309] [CK_INV:0]
  • LATCH_OR_FF=[FF:309]
  • SYNC_ATTR=[ASYNC:154] [SYNC:155]
SLICEL_CFF
  • CFFINIT=[INIT0:449] [INIT1:2]
  • CFFSR=[SRLOW:449] [SRHIGH:2]
  • CK=[CK:451] [CK_INV:0]
  • LATCH_OR_FF=[FF:451]
  • SYNC_ATTR=[ASYNC:246] [SYNC:205]
SLICEL_DFF
  • CK=[CK:312] [CK_INV:0]
  • DFFINIT=[INIT0:311] [INIT1:1]
  • DFFSR=[SRLOW:311] [SRHIGH:1]
  • LATCH_OR_FF=[FF:312]
  • SYNC_ATTR=[ASYNC:174] [SYNC:138]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
IOB
  • I=12
  • O=24
  • PAD=36
IOB_IINV
  • IN=1
  • OUT=1
IOB_INBUF
  • OUT=12
  • PAD=12
IOB_OUTBUF
  • IN=24
  • OUT=24
IOB_PAD
  • PAD=36
OLOGIC
  • D1=2
  • OQ=2
OLOGIC_O1USED
  • 0=2
  • OUT=2
RAMB18X2
  • ADDRAL10=2
  • ADDRAL11=2
  • ADDRAL12=2
  • ADDRAL13=2
  • ADDRAL14=2
  • ADDRAL15=2
  • ADDRAL4=2
  • ADDRAL5=2
  • ADDRAL6=2
  • ADDRAL7=2
  • ADDRAL8=2
  • ADDRAL9=2
  • ADDRBL10=2
  • ADDRBL11=2
  • ADDRBL12=2
  • ADDRBL13=2
  • ADDRBL14=2
  • ADDRBL15=2
  • ADDRBL4=2
  • ADDRBL5=2
  • ADDRBL6=2
  • ADDRBL7=2
  • ADDRBL8=2
  • ADDRBL9=2
  • CLKAL=2
  • CLKBL=2
  • DIAL0=2
  • DIAL1=2
  • DIAL2=2
  • DIAL3=2
  • DIAL4=2
  • DIAL5=2
  • DIAL6=2
  • DIAL7=2
  • DIPAL0=2
  • DOBL0=2
  • DOBL1=2
  • DOBL2=2
  • DOBL3=2
  • DOBL4=2
  • DOBL5=2
  • DOBL6=2
  • DOBL7=2
  • ENAL=2
  • ENBL=2
  • REGCEAL=2
  • REGCEBL=2
  • REGCLKAL=2
  • REGCLKBL=2
  • SSRAL=2
  • SSRBL=2
  • WEAL0=2
  • WEAL1=2
  • WEAL2=2
  • WEAL3=2
  • WEBL0=2
  • WEBL1=2
  • WEBL2=2
  • WEBL3=2
  • WEBL4=2
  • WEBL5=2
  • WEBL6=2
  • WEBL7=2
RAMB18X2_RAMB18X2_LOWER
  • ADDRAL10=2
  • ADDRAL11=2
  • ADDRAL12=2
  • ADDRAL13=2
  • ADDRAL14=2
  • ADDRAL15=2
  • ADDRAL4=2
  • ADDRAL5=2
  • ADDRAL6=2
  • ADDRAL7=2
  • ADDRAL8=2
  • ADDRAL9=2
  • ADDRBL10=2
  • ADDRBL11=2
  • ADDRBL12=2
  • ADDRBL13=2
  • ADDRBL14=2
  • ADDRBL15=2
  • ADDRBL4=2
  • ADDRBL5=2
  • ADDRBL6=2
  • ADDRBL7=2
  • ADDRBL8=2
  • ADDRBL9=2
  • CLKAL=2
  • CLKBL=2
  • DIAL0=2
  • DIAL1=2
  • DIAL2=2
  • DIAL3=2
  • DIAL4=2
  • DIAL5=2
  • DIAL6=2
  • DIAL7=2
  • DIPAL0=2
  • DOBL0=2
  • DOBL1=2
  • DOBL2=2
  • DOBL3=2
  • DOBL4=2
  • DOBL5=2
  • DOBL6=2
  • DOBL7=2
  • ENAL=2
  • ENBL=2
  • REGCEAL=2
  • REGCEBL=2
  • REGCLKAL=2
  • REGCLKBL=2
  • SSRAL=2
  • SSRBL=2
  • WEAL0=2
  • WEAL1=2
  • WEAL2=2
  • WEAL3=2
  • WEBL0=2
  • WEBL1=2
  • WEBL2=2
  • WEBL3=2
  • WEBL4=2
  • WEBL5=2
  • WEBL6=2
  • WEBL7=2
SLICEL
  • A=779
  • A1=622
  • A2=855
  • A3=951
  • A4=1084
  • A5=1133
  • A6=1154
  • AMUX=30
  • AQ=496
  • AX=310
  • B=694
  • B1=568
  • B2=703
  • B3=825
  • B4=959
  • B5=1000
  • B6=1018
  • BQ=309
  • BX=147
  • C=502
  • C1=507
  • C2=640
  • C3=716
  • C4=821
  • C5=852
  • C6=867
  • CE=561
  • CIN=16
  • CLK=600
  • CMUX=57
  • COUT=16
  • CQ=451
  • CX=277
  • D=525
  • D1=412
  • D2=545
  • D3=665
  • D4=775
  • D5=817
  • D6=828
  • DMUX=2
  • DQ=312
  • DX=145
  • SR=410
SLICEL_A5LUT
  • A3=1
  • A4=2
  • O5=21
SLICEL_A6LUT
  • A1=622
  • A2=855
  • A3=950
  • A4=1084
  • A5=1133
  • A6=1154
  • O6=1156
SLICEL_AFF
  • CE=466
  • CK=496
  • D=496
  • Q=496
  • SR=329
SLICEL_B5LUT
  • O5=18
SLICEL_B6LUT
  • A1=568
  • A2=703
  • A3=825
  • A4=959
  • A5=1000
  • A6=1018
  • O6=1018
SLICEL_BFF
  • CE=289
  • CK=309
  • D=309
  • Q=309
  • SR=266
SLICEL_C5LUT
  • O5=14
SLICEL_C6LUT
  • A1=507
  • A2=640
  • A3=716
  • A4=821
  • A5=852
  • A6=867
  • O6=871
SLICEL_CARRY4
  • CIN=16
  • CO3=16
  • CYINIT=8
  • DI0=24
  • DI1=24
  • DI2=18
  • DI3=16
  • O0=24
  • O1=24
  • O2=24
  • O3=18
  • S0=24
  • S1=24
  • S2=24
  • S3=18
SLICEL_CFF
  • CE=430
  • CK=451
  • D=451
  • Q=451
  • SR=324
SLICEL_CYINITGND
  • 0=6
SLICEL_D5LUT
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • O5=14
SLICEL_D6LUT
  • A1=410
  • A2=543
  • A3=663
  • A4=773
  • A5=815
  • A6=828
  • O6=830
SLICEL_DFF
  • CE=296
  • CK=312
  • D=312
  • Q=312
  • SR=238
SLICEL_F7AMUX
  • 0=157
  • 1=157
  • OUT=157
  • S0=157
SLICEL_F7BMUX
  • 0=134
  • 1=134
  • OUT=134
  • S0=134
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc5vlx50-ff324-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx50-ff324-2 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
_impact 146 91 0 0 0 0 0
bitgen 237 236 0 0 0 0 0
bitinit 2 2 0 0 0 0 0
cse_server 56 55 0 0 0 0 0
edif2ngd 4 4 0 0 0 0 0
elfcheck 4 4 0 0 0 0 0
libgen 1 1 0 0 0 0 0
map 273 259 0 0 0 0 0
netgen 91 91 0 0 0 0 0
ngcbuild 206 206 0 0 0 0 0
ngdbuild 270 269 0 0 0 0 0
par 253 253 0 0 0 0 0
platgen 1 1 0 0 0 0 0
psf2Edward 1 1 0 0 0 0 0
simgen 2 2 0 0 0 0 0
trce 252 252 0 0 0 0 0
xdsgen 1 1 0 0 0 0 0
xps 18 6 0 0 0 0 0
xst 478 462 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2014-05-31T21:14:53
PROP_intWbtProjectID=FE82185B5D4442ACA24B771B8AC44E0F PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=false PROP_DevFamily=Virtex5
PROP_DevDevice=xc5vlx50 PROP_DevFamilyPMName=virtex5
PROP_DevPackage=ff324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-2 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=73 NGDBUILD_NUM_FDCE=373 NGDBUILD_NUM_FDE=667
NGDBUILD_NUM_FDP=12 NGDBUILD_NUM_FDRE=697 NGDBUILD_NUM_FDSE=130 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=11 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=16 NGDBUILD_NUM_LUT1=62
NGDBUILD_NUM_LUT2=362 NGDBUILD_NUM_LUT3=412 NGDBUILD_NUM_LUT4=413 NGDBUILD_NUM_LUT5=638
NGDBUILD_NUM_LUT6=2105 NGDBUILD_NUM_MUXCY=82 NGDBUILD_NUM_MUXF7=291 NGDBUILD_NUM_OBUF=24
NGDBUILD_NUM_RAMB18=2 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=90
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FDC=73 NGDBUILD_NUM_FDCE=373 NGDBUILD_NUM_FDE=667
NGDBUILD_NUM_FDP=12 NGDBUILD_NUM_FDRE=697 NGDBUILD_NUM_FDSE=130 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=11 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=16 NGDBUILD_NUM_LUT1=62
NGDBUILD_NUM_LUT2=362 NGDBUILD_NUM_LUT3=412 NGDBUILD_NUM_LUT4=413 NGDBUILD_NUM_LUT5=638
NGDBUILD_NUM_LUT6=2105 NGDBUILD_NUM_MUXCY=82 NGDBUILD_NUM_MUXF7=291 NGDBUILD_NUM_OBUF=24
NGDBUILD_NUM_RAMB18=2 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=90