System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
Path C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
C:\VXIPNP\WINNT\BIN;
C:\VXIPNP\WINNT\TekVISA\BIN;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin\;
C:\Program Files\IVI Foundation\VISA\WinNT\TekVISA\BIN;
C:\Program Files\MATLAB\R2011a\runtime\win32;
C:\Program Files\MATLAB\R2011a\bin
C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
C:\VXIPNP\WINNT\BIN;
C:\VXIPNP\WINNT\TekVISA\BIN;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin\;
C:\Program Files\IVI Foundation\VISA\WinNT\TekVISA\BIN;
C:\Program Files\MATLAB\R2011a\runtime\win32;
C:\Program Files\MATLAB\R2011a\bin
C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
C:\VXIPNP\WINNT\BIN;
C:\VXIPNP\WINNT\TekVISA\BIN;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin\;
C:\Program Files\IVI Foundation\VISA\WinNT\TekVISA\BIN;
C:\Program Files\MATLAB\R2011a\runtime\win32;
C:\Program Files\MATLAB\R2011a\bin
C:\Xilinx\12.4\ISE_DS\ISE\\lib\nt;
C:\Xilinx\12.4\ISE_DS\ISE\\bin\nt;
C:\Xilinx\12.4\ISE_DS\PlanAhead\bin;
C:\Xilinx\12.4\ISE_DS\ISE\bin\nt;
C:\Xilinx\12.4\ISE_DS\ISE\lib\nt;
C:\Xilinx\12.4\ISE_DS\EDK\bin\nt;
C:\Xilinx\12.4\ISE_DS\EDK\lib\nt;
C:\Xilinx\12.4\ISE_DS\common\bin\nt;
C:\Xilinx\12.4\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\System32\Wbem;
C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;
C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;
C:\VXIPNP\WINNT\BIN;
C:\VXIPNP\WINNT\TekVISA\BIN;
C:\Program Files\IVI Foundation\VISA\WinNT\Bin\;
C:\Program Files\IVI Foundation\VISA\WinNT\TekVISA\BIN;
C:\Program Files\MATLAB\R2011a\runtime\win32;
C:\Program Files\MATLAB\R2011a\bin
XILINX C:\Xilinx\12.4\ISE_DS\ISE\ C:\Xilinx\12.4\ISE_DS\ISE\ C:\Xilinx\12.4\ISE_DS\ISE\ C:\Xilinx\12.4\ISE_DS\ISE\
XILINXD_LICENSE_FILE D:\xilinx files\Crack\license\license.lic D:\xilinx files\Crack\license\license.lic D:\xilinx files\Crack\license\license.lic D:\xilinx files\Crack\license\license.lic
XILINX_DSP C:\Xilinx\12.4\ISE_DS\ISE C:\Xilinx\12.4\ISE_DS\ISE C:\Xilinx\12.4\ISE_DS\ISE C:\Xilinx\12.4\ISE_DS\ISE
XILINX_EDK C:\Xilinx\12.4\ISE_DS\EDK C:\Xilinx\12.4\ISE_DS\EDK C:\Xilinx\12.4\ISE_DS\EDK C:\Xilinx\12.4\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\12.4\ISE_DS\PlanAhead C:\Xilinx\12.4\ISE_DS\PlanAhead C:\Xilinx\12.4\ISE_DS\PlanAhead C:\Xilinx\12.4\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   CHIP_SASEBO_GII_AES_Comp.prj  
-ifmt   mixed MIXED
-ofn   CHIP_SASEBO_GII_AES_Comp  
-ofmt   NGC NGC
-p   xc5vlx50-2-ff324  
-top   CHIP_SASEBO_GII_AES_Comp  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO NO
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-dsp_utilization_ratio DSP Utilization Ratio 100 100%
-reduce_control_sets   Off OFF
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-use_dsp48   Auto AUTO
-iobuf   YES YES
-max_fanout   100000 100000
-bufg   32 32
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Auto AUTO
-use_sync_set   Auto AUTO
-use_sync_reset   Auto AUTO
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc5vlx50-ff324-2 None
-uc   D:/Suvadeep/DRECON_AES_Prev/pin_sasebo_gii.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-ir Use RLOC Constraints OFF OFF
-t Starting Placer Cost Table (1-100) Map 1 0
-cm Optimization Strategy (Cover Mode) area area
-intstyle   ise None
-lc LUT Combining off off
-o   CHIP_SASEBO_GII_AES_Comp_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc5vlx50-ff324-2 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise  
-mt Enable Multi-Threading off off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2926 MHz Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2926 MHz Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2926 MHz Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2926 MHz
Host iit-db4792ffdd7 iit-db4792ffdd7 iit-db4792ffdd7 iit-db4792ffdd7
OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional
OS Release Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600)