CHIP_SASEBO_GII_AES_Comp Project Status
Project File: DRECON_AES.xise Parser Errors: No Errors
Module Name: CHIP_SASEBO_GII_AES_Comp Implementation State: New
Target Device: xc5vlx50-2ff324
  • Errors:
No Errors
Product Version:ISE 12.4
  • Warnings:
272 Warnings (272 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,568 28,800 5%  
    Number used as Flip Flops 1,568      
Number of Slice LUTs 3,877 28,800 13%  
    Number used as logic 3,871 28,800 13%  
        Number using O6 output only 3,807      
        Number using O5 output only 58      
        Number using O5 and O6 6      
    Number used as exclusive route-thru 6      
Number of route-thrus 65      
    Number using O6 output only 62      
    Number using O5 output only 3      
Number of occupied Slices 1,381 7,200 19%  
Number of LUT Flip Flop pairs used 4,251      
    Number with an unused Flip Flop 2,683 4,251 63%  
    Number with an unused LUT 374 4,251 8%  
    Number of fully used LUT-FF pairs 1,194 4,251 28%  
    Number of unique control sets 50      
    Number of slice register sites lost
        to control set restrictions
48 28,800 1%  
Number of bonded IOBs 36 220 16%  
    Number of LOCed IOBs 36 36 100%  
Number of BlockRAM/FIFO 2 48 4%  
    Number using BlockRAM only 2      
        Number of 18k BlockRAM used 2      
    Total Memory used (KB) 36 1,728 2%  
Number of BUFG/BUFGCTRLs 2 32 6%  
    Number used as BUFGs 2      
Average Fanout of Non-Clock Nets 5.44      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat May 31 21:40:16 20140267 Warnings (267 new)259 Infos (259 new)
Translation ReportCurrentSat May 31 21:40:22 2014000
Map ReportCurrentSat May 31 21:41:16 201405 Warnings (5 new)8 Infos (8 new)
Place and Route ReportCurrentSat May 31 21:41:46 2014000
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentSat May 31 21:41:58 2014002 Infos (2 new)
Bitgen ReportCurrentSat May 31 21:42:26 2014001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSat May 31 21:42:26 2014
WebTalk Log FileCurrentSat May 31 21:42:28 2014

Date Generated: 06/08/2014 - 11:04:38