Department of Computer Science and Engineering
Indian Institute of Technology (IIT) Kharagpur
Kharagpur, West Bengal - 721302, India
Phone: +91-3222-281431/+91 9433244530
Email: ckarfa @ cse.iitkgp.ernet.in
[ Research |
Work Experience |
High-level Synthesis, Formal Verification, Embedded System Design and Verification
Supervisor: Prof. C. R. Mandal and
Prof. D. Sarkar
- Chandan Karfa}, Dipankar Sarkar, Chittaranjan Mandal, ``Verification and Synthesis of Digital Circuits:
High-level Synthesis and Equivalence Checking, LAMBERT Academic Publishing, August 2010 (ISBN 978-3-8383-9813-6).
- C. Karfa, D. Sarkar, C Mandal. ``Verification of Sequential to Parallel Code Transformations'' (Communicated)
- C. Karfa, D. Sarkar, C Mandal. ``Formal Verification of Code Motion Techniques using Data-flow Driven Equivalence Checking'' (Communicated)
- C. Karfa, D. Sarkar, C Mandal. ``Verification of Datapath and Controller Generation Phase in High-level Synthesis of Digital Circuits'', in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and page 479-492, Vol. 29, No. 3, March, 2010. (Link)
- C. Karfa, D. Sarkar, C Mandal, P. Kumar. ``An Equivalence Checking Method for Scheduling Verification in High-level Synthesis'', in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems, page 556-569, Vol 27, No. 3, March, 2008. (Link)
- C. Karfa, D. Sarkar, C Mandal, ``Verification of Loop and Arithmetic Transformations Applied on Array-Intensive Behaviours'' (communicated).
- C. Karfa, D. Sarkar, C Mandal, ``Verification of Register Transfer Level Low Power Transformations'' in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011 (Accepted).
- C. Karfa, K Banerjee, D. Sarkar, C Mandal, ``Equivalence Checking of Array-Intensive Programs'' in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011 (Accepted).
- C. Karfa, D. Sarkar, C Mandal, ``Data-flow Driven Equivalence Checking for Verification of Code Motion Techniques'' in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2010, Lixouri Kefalonia, Greece, pp 428-433, July 5-7, 2010.
- C. Karfa, D. Sarkar, C Mandal, ``Verification of Data-path and Controller Generation Phase in High-level Synthesis''. In 15th IEEE International Conference on Advanced Computing and Communication (ADCOM 2007), page 315-320, December 17-19, India, 2007.
- C. Karfa, D. Sarkar and C Mandal, ``Hand-in-hand Verification of High-level Synthesis'' in 17th edition of ACM Great Lakes Symposium on VLSI 2007 (GLSVLSI'07), page 429-434, March 11-13, Stresa, Italy.(Link)
- C. Karfa, C. Mandal, D. Sarkar, C. Reade, ``Register Sharing Verification during Data-path Synthesis'', in IEEE International Conference on Computing: Theory and Application 2007 (ICCTA'07), page 135-140, March 5-7, Kolkata, India, 2007.(Link)
- C. Karfa, C. Mandal, D. Sarkar, S. R. Pentakota, C. Reade, ``A Formal Verification Method of Scheduling in High-level Synthesis'', in 7th IEEE International Symposium on Quality Electronic Design (ISQED'06), page 71-76. San Jose, CA, USA, 2006.(Link)
- S. Biswas, C. Karfa, H. Kanwar, D.Sarkar, S. Mukhopadhyay A. Patra, ``Fairness of Transitions in Diagnosability Analysis of Hybrid Systems'', in American Control Conference, 2006 (ACC'06), page 2664-2669, USA, 2006. (Link)
- C. Karfa, C. Mandal, D. Sarkar, S. R. Pentakota, C. Reade. ``Verification of Scheduling in High-level Synthesis'', in IEEE Computer Society Annual Symposium on VLSI (ISVLSI¿06). Page 141-146, March 2-3, Karlsruhe, Germany, 2006.
- C. Karfa, J. S. Reddy, S. Biswas, C. R. Mandal, D. Sarkar, ``SAST: An Interconnection aware high level synthesis tool'', in 9th VLSI Design and Test (VDAT'05), Page 285-293. August 10-13, Bangalore, India, 2005.
- Reviewer: VLSID'07, VDAT'08, TechSym'10, ISVLSI'11 and Journal of Electrical and Electronics Engineering Research
- Teaching Assistant for Operating Systems Lab under Prof. P. Dasgupta and Prof. G. Biswas (Autumn'05)
- Teaching Assistant for Programming and Data Structure Lab under Prof. C. Mandal and Prof. P. S. Dey (Spring'05), Prof. D. Sarkar and Prof. D. Roychowdhury (Spring'06) and under Prof. P. Mitra (Autumn'08)
- Teaching Assistant for Computing Systems Lab under Prof. A. Gupta and Prof. A. Das (Autumn'07)
- Teaching Assistant for Theory of Computation/Formal Systems under Prof. D. Sarkar (Spring'09) (Spring'10)
- Teaching Assistant for Logics for Computer Science under Prof. D. Sarkar (Autumn'09) (Autumn'10)
- Teaching Assistant for CAD for VLSI under Prof. C. Mandal (Spring'11)
- A graph theoretic approach for two layer no-dogleg channel routing problem to minimize total wire length:
We considered the reserved two-layer Manhattan routing model of channel where horizontal wire segments and the vertical wire segments are placed into two different layers. We formulated and implemented a sandwich approach of assigning nets to the tracks as our algorithm assign nets to the top (current) and to the bottom (current) in alternative iterations. The algorithm based on track assignment heuristic where a tuple of weights in a logical sequence of priority are assigned to the nets. This project has been implemented in C in windows machine.
- High Level Synthesis and Verification of Digital Circuits:
We have developed a High-level synthesis (HLS) tool called Structured Architecture Synthesis Tool (SAST). This tool takes restricted class of C programs and the architectural parameter of the structured data-path and produces register transfer level (RTL) design having distinct control-path and data-path partition in Verilog. The SAST is an interconnection aware HLS tool in the sense that it produces structured data-path by avoiding random interconnections among the data-path components. It supports pipelined and multi-cycle operations. The verification of the different phases of the HLS is performed hand-in-hand with the synthesis process in SAST. Our verification method is based on the equivalence checking of two finite state machines with data-path (FSMDs). The tool automatically generates the FSMD from the input and output of each phase at the end of this phase and verification is performed to check the correctness of that phase. The tool is implemented in C in Linux environment.
- Advanced VLSI Design. Advanced VLSI Design Laboratory, IIT Kharagpur (May 2005 - June 2005)
- Aunwesha Knowledge Technology Solutions, Salt Lake, Kolkata (May 2003 - June 2003)
- B.Tech. in Information Technology from University Science Instrumentation Center, University of Kalyani (2004).
- Percentage: 89.2%
- Thesis: A graph theoretic approach for two layer no-dogleg channel routing problem to minimize total wire length
- MS (by Research) from Indian Institute of Technology (IIT) Kharagpur (2007)
- CGPA: 9.79
- Thesis: Hand-in-hand Verification and Synthesis of Digital Circuits
- Pursuing PhD in Department of Computer Science & Engineering, Indian Institute of Technology Kharagpur
- Thesis: Formal Verification of Behavioural Transformations Encountered in Embedded System Design
- Third prize in the Poster Contest in TechVista 2010, Microsoft Research India's annual research symposium
- First prize in the EDA software contest in the 22nd international conference on VLSI design and embedded systems
- Recipient of Microsoft Research India PhD Fellowship for the period 2008-2012
- Innovative Student Projects Award ¿ 2008 (Master Level) for MS thesis work by Indian National Academy of Engineering (INAE)
- Student Best Paper Award in 15th International Conference on Advanced Computing and Communications (ADCOM 2007)
- ACM/SIGDA Travel Grant and Institute travel grant for visiting GLSVLSI 2007
- Runner up position in the national level and the winner position in the Eastern Region in the Young IT Professional 2007 contest organized by the Computer Society of India (with Somnath Dey)
- Finalist in Intel India Student Research Contest (IISRC) 2005-06
- National scholarship for the talented children in rural areas in the year 1996
Last updated: April 10, 2011