Transistor sizing to achieve desired performance parameters is an important design challenge. Accurate modelling is essential for parameter optimisation. This thesis presents hybrid modelling of CMOS circuits at level 2 and modelling complex CMOS circuits at a higher level i.e. level 49, parameter optimisation and determination of performance parameters (rise time, fall time and power dissipation).

The work in this thesis first models the circuit to be analysed through a set of differential equations based on the behaviour of the transistors and their interconnections. Simple ODE modelling isn’t adequate as the transistors may be in various states (cutoff, linear, saturation). Accordingly, a circuit with n transistors may have up to 3n states. As the circuit operates, it makes transitions between these states (also called locations). ODE modelling is inadequate to capture this kind of situation. To handle this, the modeling of CMOS circuits have been done as a Stateflow model in Matlab Simulink. The standard equations which govern nMOS and pMOS transistors and involve the transistor geometries as parameters have been used.

As a number of locations corresponding to the regions of operations of the transistors are involved, it is important to check that all relevant transitions are adequately covered. This may be called the completeness of the model. In this thesis a mechanism is also presented to determine the completeness of the modelling of the circuit.

In each location, corresponding to the regions of operation of the transistors, Spice Level 2 model equations have been considered which include second-order effects. These equations are directly related to the specification of different parameters of the transistors. To describe different operating regions of the transistors, the differential equations have been formulated. The mechanism has been successfully demonstrated on a CMOS inverter, a CMOS NAND2 and CMOS NOR2 gate. An efficient modeling technique has been developed for CMOS circuits with separate networks of pMOS/nMOS transistors for pull-up/pull-down operations. The output waveform of the Stateflow model is displayed in a display box with respect to the simulation time. The advantage of the present modeling technique is that Stateflow models are comparable with respect to real circuit simulation results and the model evaluation time is comparatively fast.

The thesis then presents complex CMOS circuit modeling in MATLAB Simulink as Stateflow model. Modeling of a precharge based circuit using higher level model equations has been done. To determine the accuracy of the model that depends on the equations governing the behaviour of the MOSFETs, BSIM3v3 level49 equations have been considered. It also depends on the influence of the various model parameters. An efficient modeling technique has been developed for CMOS circuit with a precharge based circuit with separate pMOS/nMOS networks. The model’s completeness and circuit performance requirements are formulated and reachability analysis has been performed on the model. The benefit of the present modeling technique is that Stateflow model is comparable with respect to real circuit simulation results. Though the model uses complex circuit equations, evaluation time is comparatively fast.

This thesis then presents an application of SAT based tool to find optimal values of the relevant parameters to achieve a specified circuit performance. Signal temporal logic (STL) formulas are used to specify the desired properties of continuous signals determining the parameters of the underlying model. Two optimisation algorithm have been used Nelder Mead (NM) algorithm of Breach tool and a 2D search algorithm. The circuit performance is optimised through finding a range of admissible circuit parameters. Results obtained from Breach can be visualised through Matlab Simulink. An efficient optimisation technique has been developed for CMOS circuits that determine the transistor parameters. The advantage of the optimisation technique is that a range of admissible circuit parameters are obtained.

This thesis finally presents experimentations on CMOS inverter, NAND2, NOR2 and precharge based circuit. The effectiveness of the above modeling technique has been demonstrated with a set of experimental results. The CMOS circuits have been redesigned using Spice simulator with synthesized transistor size values obtained using optimisation algorithms. Results obtained from NM and 2D search algorithms are comparable with the Spice results.