Power analysis attacks (PAAs) have been found to be extremely effective on cryptographic systems to derive the cryptographic secrets from these traces. In this work, Binary Decision Diagram (BDD) based dual-rail logic circuit schemes have been developed to counter power analysis attacks (PAAs). The hallmark of our circuit schemes is that an identical number of switchings is ensured on each circuit path. The transistors are interconnected to create pull-up and pull-down paths to outputs by way of binary decisions based on the input variables, so as to realise the required Boolean function. This principle of operation has directly permitted the use of BDD based logic synthesis to design the required pull-up and pull-down networks of transistors. The operation of these circuit schemes feature novel pre-charge generation, voltage scaling with leakage power minimization and early propagation effect resistance mechanism. In particular, we have developed and explored top pre-charging, top-bottom pre-charging, bottom pre-charging and symmetric NMOS bottom pre-charging logics. A simple synthesis algorithm for mapping a given Boolean functions to such BDD based circuits is also presented. Extensive experimentation has been carried out to establish resistance of our circuits to PAAs. Objective of the experimentation is two fold, to demonstrate resistance to power attacks and to highlight the low power characteristics. Towards the first objective, differential power attacks such as, difference of mean (DoM) and correlation power attack (CPA) have been carried out. Resilience to the the early propagation effect (EPE) is also demonstrated. Six 2-input basic cell and two 4×4 S-boxes are used for experimental benchmark. Experimental results on circuits with bottom pre-charge logic demonstrate a significant reduction by 99.68% and 88.55% in peak power variance (PPV) over two chosen competing designs, for the basic cell. The reduction in PPV is recorded to be greater than 99.9% for the S-box implementations for both those design. A reduction of about 30% to 67% in both average power and average current consumption is observed while comparing with the chosen techniques. Experimental results on circuits with various other features such as top pre-charge and top-bottom pre-charge also demonstrate a large reductions in PPV. Significant reduction for average power and average current for both the pre-charge logics is also achieved. Circuits using top-pre charging required less transistors and demonstrated lower PPV in comparison with others. Symmetric NMOS bottom pre-charge logic was more resilient to EPE due to its symmetric nature. Bottom pre-charge and symmetric NMOS bottom pre-charge logic were also effective in avoiding timing attacks along with top-bottom pre-charge logic.