The growing complexity of integrated systems being designed today, together with the increasing fragility of analog components brought about by shrinking geome tries and reduced power consumption, pose severe challenges to traditional analog integrated circuit (IC) designers to produce satisfactory results in a short time. In order to improve the analog design quality and reduce the design time, the new analog design methodologies are hierarchically divided into several abstraction levels. High-level design of analog systems is an important step in an analog design automation process. This motivates us to develop methodologies which make several tasks of the analog high-level design process fast and accurate. This thesis presents optimization-based methodologies for the task of high-level performance model generation, optimal component-level topology generation and high-level specification translation.

This thesis first presents a non parametric regression-based methodology for the generation of high-level performance models for analog component blocks. The transistor sizes of the circuit-level implementations of the component blocks define the sample space. Performance data are generated through SPICE simulation. Least squares support vector machine (LS-SVM) is used as regression function. Optimal values of the model hyper parameters are determined through grid search technique and a GA-based technique. The constructed performance models are used within a GA-based topology sizing process. The entire methodology has been demonstrated with numerical examples.

This thesis then presents a top-down methodology for the generation of an optimal component-level topology for linear analog systems. The topologies are generated from a transfer function model of the system via state space matrix models. The topology exploration process is modeled as a state space matrix exploration process. Simulated annealing based optimization procedure determines an optimal state space model which is subsequently realized by appropriate analog component blocks to generate an optimal component-level topology. As a case study, the thesis presents a methodology for generation of an operational transconductance amplifier (OTA)-capacitor (C) based topology for continuous-time sigma-delta modulator.

The thesis finally presents a methodology for the task of high-level specification translation. A meet-in-the-middle approach is followed for the construction of the feasible design space. Least squares support vector machine (LS-SVM) technique is used to identify an accurate geometry of the actual feasible design space. Genetic algorithm (GA) is used to explore the feasible design space. The effectiveness of the procedure is illustrated with numerical examples.

These methodologies form the core of an semi-automated tool for analog high-level design. The methodologies have been implemented under Matlab-Simulink environment. For demonstration of the methodologies, we choose two case studies: interface electronics for MEMS capacitive accelerometer sensor and continuous time modulator system. Optimal topologies for these two systems have been generated and specification parameters of the component blocks have been determined using the present methodologies. Finally they have been implemented at the transistor level and are simulated with SPICE. The SPICE simulation results satisfy the desired specifications of the system and matches closely with the predicted results. This validates the entire procedure.