Hand-in-hand Verification and Synthesis of Digital Circuits
Chandan Karfa
Abstract
     

Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go hand-in-hand with each phase of synthesis with scope to handle the specialties of each synthesis sub-task separately. This thesis is concerned with hand-in-hand verification and (high-level) synthesis of digital circuits. The verification of high-level synthesis is performed in three-phases namely, scheduling verification, allocation and binding verification and data-path and controller verification. The input and output of each phase are represented as finite state machines with data-paths (FSMD); the equivalence of two FSMDs is defined and has been proved. The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. The scheduling verification method is strong enough to accommodate merging of path segments in the original behaviour, application of several code motion techniques and some arithmetic transformations employed during scheduling. The allocation and binding verification method is capable of handling register sharing verification. For verification of the data-path and controller synthesis phase, a rewriting method is proposed. The method reveals, from a flat set of control signal assertions, the spatial sequences of data flow over the data-path, each sequence realizing a member of a concurrent set of register transfer operations. A high-level synthesis tool, called structured architecture synthesis tool (SAST), has been developed which support hand-in-hand synthesis and verification. The synthesis flow of SAST and the results for several high-level synthesis benchmarks are provided. The thesis concludes by identifying some directions for future research.

     
     
     
Keywords: High-level Synthesis, Formal Verification, Equivalence Checking, Normalization, FSMD models, Path-Based Scheduling, Code Motion Techniques, Allocation and Binding, Register Sharing, Data-Path and Controller Generation, Rewriting Method, SAST.


     
chitta@iitkgp.ac.in [Publications list]