Publications of Chittaranjan Mandal

Journal Publications

  1. DigiLoCS: A Leap Forward in Predictive Organ-on-Chip Simulations, PLOS ONE, pp –, vol –, no –, Oct 2024, Manoja RA, Chittaranjan Mandal, Alex Pothen, Stephan Schaller, Christian Maass
  2. Parameter estimation for the oral minimal model and parameter distinctions between obese and non-obese type 2 diabetes, DNA and Cell Biology Reports, Mary Ann Liebert, pp 15–27, vol 5, no 1, 2024Oct7, Manoja RA, Devleena Ghosh, Chittaranjan Mandal, KV Venkatesh, Jit Sarkar, Partha Chakrabarti, Sujay K Maity
  3. SMT based parameter identifiable combination detection for non-linear continuous and hybrid dynamics, ACM Journal on Formal Aspects of Computing: Applicable Formal Methods (FAC), article 15, pages 41, vol 36, no 3, Sep 2024, Devleena Ghosh, Chittaranjan Mandal
  4. Energy-Aware Service Allocation: A Crow Search-Based Approach, IEEE Trans on Green Comms and Networking - Area 2: Green Wireless Comms and Networking, pp 211–223, vol. 7, no. 1, Oct 2022; Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal
  5. SeamFlow: Seamless Flow Forwarding in Energy Harvesting-Enabled Access Points of SDWLAN, IEEE Transactions on Sustainable Computing, pp 94–108, vol. 8, no. 1, Jan-Mar 2023; Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal, Samaresh Bera
  6. Sustainable Maintenance of Connected Dominating Set by Solar Energy Harvesting for IoT Networks, IEEE Trans on Green Commus and Networking - Area 3: Green Internet of Things and Energy-harvesting Comms, pp 2115–2127, vol. 6, no. 4, Dec 2022; Chandrani Ray Chowdhury, Chittaranjan Mandal, Sudip Misra
  7. Translation Validation of Coloured Petri Net Models of Programs on Integers, Acta Informatica, Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal, Holger Giese
  8. Distinct patho-clinical clusters among uncontrolled type 2 diabetes patients: Results from a prospective study in rural India, BMJ Open Diabetes Research & Care, vol. 10, no. 1, Feb 2022; Manoja RA, Sujay Krishna Maity, Avishek Paul, Partha Chakrabarti, Chittaranjan Mandal, Jit Sarkar
  9. ETHoS: Energy-Aware Traffic Engineering for Sustainable Hybrid SDN, IEEE Transactions on Sustainable Computing, pp 875–886, vol. 7, no. 4, Oct-Dec 2022; Ilora Maity, Sudip Misra, Chittaranjan Mandal
  10. SCOPE: Cost-Efficient QoS-Aware Switch and Controller Placement in Hybrid SDN, IEEE Systems Journal, pp 4873–4880, vol. 16, no. 3, Sept 2022; Ilora Maity, Sudip Misra, Chittaranjan Mandal
  11. IEEE 802.11k-based Lightweight, Distributed and Cooperative Access Point Coverage Estimation Scheme in IoT Networks, IEEE Internet of Things Journal, pp 10139–10148 vol. 9, no. 12, June 2022; Chandrani Ray Chowdhury, Sudip Misra, Chittaranjan Mandal
  12. CORE: Prediction-Based Control Plane Load Reduction in Software-Defined IoT Networks, IEEE Transactions on Communications, pp 1835–1844, vol. 69, no. 3, March 2021; Ilora Maity, Sudip Misra, Chittaranjan Mandal
  13. DART: Data Plane Load Reduction for Traffic Flow Migration in SDN, IEEE Transactions on Communications, pp 1765–1774, vol. 69, no. 3, March 2021; Ilora Maity, Sudip Misra, Chittaranjan Mandal
  14. Secure path balanced BDD based pre-charge logic for masking, IEEE Transactions on Circuits and Systems I, pp 4747–4760, vol. 67, no. 12, Dec 2020; Partha De, Udaya Parampalli, Chittaranjan Mandal
  15. Clustering Based Parameter Estimation of Thyroid Hormone Pathway, IEEE/ACM Transactions on Computational Biology and Bioinformatics, pp 343–354, vol. 19, no. 1, Feb 2022; Devleena Ghosh, Chittaranjan Mandal
  16. Automatic Generation of Route Control Chart from Validated Signal Interlocking Plan, IEEE Transactions on Intelligent Transportation Systems, pp 6516–6525, vol. 22, no. 10, Oct 2021; Arindam Das, Manoj Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M M Waris (tool slide show)
  17. Verification of Parallelizing Transformations of KPN Models, IET Cyber-Physical Systems: Theory and Applications, pp 276–289, vol. 4, no. 3, Mar 2019; Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
  18. Path Balanced Logic Design to Realise Block Ciphers Resistant to Power and Timing Attacks, IEEE Transactions on VLSI, pp 1080–1092, vol. 27, no. 5, May 2019; Partha De, Chittaranjan Mandal, Udaya Parampalli
  19. Tensor-Based Rule-Space Management System in SDN, IEEE Systems Journal, pp 3921–3928, vol. 13, no. 4, December 2019; Ilora Maity, Ayan Mondal, Sudip Misra, Chittaranjan Mandal
  20. Equivalence Checking of Petri net Models of Programs using Static and Dynamic Cut-points, Acta Informatica, vol 56, pp 321–383, 2019, Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
  21. CURE: Consistent Update with Redundancy Reduction in SDN, IEEE Transactions on Communications, pp 3974–3981, vol. 66, no. 9, April 2018; Ilora Maity, Ayan Mondal, Sudip Misra, Chittaranjan Mandal
  22. COLDVL: A Virtual Laboratory Tool with Novel Features to Support Learning in Logic Design and Computer Organisation, Journal of Computers in Education, pp 461–490, vol. 4, no. 4, Dec 2017; Gargi Roy, Devleena Ghosh, Chittaranjan Mandal
  23. Refresh Re-Use based Transparent Test for Detection of In-Field Permanent Faults in DRAMs, Integration, the VLSI Journal, pp 168–178, vol. 59, July 2017; Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta
  24. Distributed Construction of Minimum Connected Dominating Set in Wireless Sensor Network Using Two-Hop Information, Computer Networks, pp 137–152, vol 123, 2017, J P Mohanty, Chittaranjan Mandal, Chris Reade
  25. Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers, IEEE Transactions on Software Engineering, pp 946–953, vol 43, issue 10, December 2016, Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal
  26. Deriving Bisimulation Relations from Path Based Equivalence Checkers, Formal Aspects of Computing, pp 365–379, vol 29, no 2, 2017, Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal
  27. Construction of Minimum Connected Dominating Set in Wireless Sensor Networks Using Pseudo Dominating Set, Ad Hoc Networks, pp 61–73, vol 42, 2016, J P Mohanty, Chittaranjan Mandal, Chris Reade, Ariyam Das
  28. A Path Construction Algorithm for Translation Validation using PRES+ Models, Parallel Processing Letters, pp 25, vol 26, no 02, 2016, Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal, Kunal Banerjee, K R Duddu
  29. Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs, IEEE Transactions on CAD, pp 2015--2019, vol 33, no 12, Aug 2014, Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal
  30. Verification of Code Motion Techniques using Value Propagation, IEEE Transactions on CAD, pp 1180--1193, vol 33, no 8, Aug 2014, Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
  31. Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviours, IEEE Transactions on CAD, pp 1787--1800, vol 32, no. 11, Nov, 2013, Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal.
  32. Formal Verification of Code Motion Techniques using Data-flow Driven Equivalence Checking, ACM TODAES, pp 30:1--30:37, vol. 17, no. 3, Jun 2012; Chandan Karfa, Chittaranjan Mandal and Dipankar Sarkar
  33. POWER-SIM: An SoC Simulator for Estimating Power Profiles of Mobile Workloads, Journal of Low Power Electronics (JOLPE), pp 293--303, vol. 8, no. 3, Jan 2012; P Ghosh, Aritrah Hazra, Rahul Gonnabhaktula, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan Mandal and Krishna Paul
  34. A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies, VLSI Design, vol. 2011, artID: 475952, 17 pages; May 2011; Soumya Pandit, Chittaranjan Mandal, Amit Patra.
  35. An Automated High-Level Topology Generation Procedure for Continuous-Time ΣΔ Modulator, Integration, the VLSI Journal, pp 289-304, vol. 43, no. 3, 2010; June 2010; Soumya Pandit, Chittaranjan Mandal, Amit Patra. (Abstract)
  36. Verification of Datapath and Controller Generation Phase in High-level Synthesis of Digital Circuits, IEEE Transactions on CAD, pp 479-492, vol. 29, no. 3, 2010; Mar 2010; Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal. (Abstract)
  37. Minimum Connected Dominating Set using a Collaborative Cover Heuristic for Adhoc Sensor Networks, IEEE Transactions on Parallel and Distributed Systems, pp 292-302, vol. 21, no. 3, March 2010, Rajiv Misra, Chittaranjan Mandal. (Abstract)
    1. A survey on connected dominating set construction algorithm for wireless sensor networks; Zhuo Liu, Bingwen Wang and Lejiang Guo; Information Technology Journal 9 (6): 1081-1092, 2010 ISSN 1812-5638
    2. Ant colony optimization applied to minimum weight dominating set problem, Jovanovic Raka and Tuba Milan and Simian Dana in ACMOS'10, 2010, link
    3. A Survey on Connected Dominating Set Construction Algorithm for Wireless Sensor Networks, Liu, Z. and Wang, B. and Guo, L., Information Technology Journal, v9, n6, pp 1081--1092, 2010, issn 1812-5638
    4. An Improved Greedy Construction of Minimum Connected Dominating Sets in Wireless Networks, Das, A. and Mandal, C. and Reade, C. and Aasawat, M., IEEE WCNC 2011, pp 1601-1606, Cancun, March 28-31, 2011
    5. Efficient Broadcasting in Multi-hop Wireless Networks with a Realistic Physical Layer, Wong, G.K.W. and Liu, H. and Chu, X. and Leung, Y.W. and Xie, C. in Ad Hoc Networks, pp 1570-8705, 2010, Elsevier, link
  38. Rotation of CDS via Connected Domatic Partition in Ad hoc Sensor Networks, IEEE Transactions on Mobile Computing, pp 488--499, vol. 8, no. 4, April 2009, Rajiv Misra, Chittaranjan Mandal. (Abstract)
    1. Building (1− ε) Dominating Sets Partition as Backbones in Wireless Sensor Networks Using Distributed Graph Coloring, D Mahjoub, D Matula - Distributed Computing in Sensor Systems, 2010 - Springer link
    2. VBS: maximum lifetime sleep scheduling for wireless sensor networks using virtual backbones, Y Zhao, J Wu, F Li, S Lu - INFOCOM, 2010 Proceedings IEEE, 2010 link
    3. An Improved Greedy Construction of Minimum Connected Dominating Sets in Wireless Networks, Das, A. and Mandal, C. and Reade, C. and Aasawat, M., IEEE WCNC 2011, pp 1601-1606, Cancun, March 28-31, 2011
  39. Efficient Clusterhead Rotation via Domatic Partition in Self-Organizing Sensor Networks, Wireless Communications and Mobile Computing, pp 1040--1058, vol. 9, issue 9, Aug 2009, Rajiv Misra, Chittaranjan Mandal. (Abstract)
    1. Building (1− ε) Dominating Sets Partition as Backbones in Wireless Sensor Networks Using Distributed Graph Coloring, D Mahjoub, D Matula - Distributed Computing in Sensor Systems, 2010 - Springer link
    2. Base Station Positioning and Relocation in Wireless Sensor Networks, P Dehleh Hossein Zadeh - repository.library.ualberta.ca, link
  40. A Fast Exploration Procedure for Analog High-Level Specification Translation, IEEE Transactions on CAD, pp 1493--1497, vol. 27, no. 8, August 2008; Soumya Pandit, Sumit K Bhattacharya, Chittaranjan Mandal, Amit Patra. (Abstract)
  41. An Equivalence Checking Method for Scheduling Verification in High-level Synthesis, IEEE Transactions on CAD, pp 556--569, vol. 27, no. 3, 2008; Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Pramod Kumar.
    1. Translation validation of high-level synthesis, S Kundu, S Lerner, R K Gupta; IEEE TCAD, vol 29, no 4, 2010 link
    2. Equivalence checking of scheduling with speculative code transformations in high-level synthesis, C-H Lee, C-H Shih, J-D Huang, J-Y Jou; ASPDAC'11, 2011 link
  42. A System for Automatic Evaluation of `C' Programs - features and interfaces, International Journal of Web-Based Learning and Teaching Technologies (IJWLTT), pp 24-39, vol. 2, no. 4, 2007; Amit Mandal, C Mandal, Chris Reade. (Abstract)
  43. Web-based Course management and Web Services, Electronic Journal of e-Learning, pp 128-137, vol. 2, no. 1, 2004; C Mandal, Vijaya Luxmi Sinha, Chris Reade. (Abstract / PDF paper)
    1. Listed in Educause CONNECT -- transforming education through information technologies, link
    2. An architecture solution for E-Learning System — ESSA, link
  44. Genetic Algorithms for High-Level Synthesis in VLSI Design, Materials and Manufacturing Processes, pp 355-383, vol. 18, no. 3, 2003; C. Mandal, P. P. Chakrabarti. (Abstract / PDF paper).
  45. GABIND: A Genetic Algorithm Approach to Allocation and Binding for the High-Level Synthesis of Data Paths, IEEE Transactions on VLSI, pp 747-750, vol. 8, no. 6, December 2000; C. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / PDF paper).
    1. Xuejun Tan , Bir Bhanu, Fingerprint matching by genetic algorithms, Pattern Recognition, v.39 n.3, p.465-477, March, 2006
    2. An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis Harmanani H, Saliba Rony, Journal of Circuits, Systems, and Computers, World Scientific Publishing, vol 14, no 2, pp 347-366, April 2005
    3. Scheduling and allocation using closeness tables, Burns, F. Shang, D. Koelmans, A. Yakovlev, A., Proceedings of the IEE, Computers and Digital Techniques, pp 332-340, vol 151, issue 5, Sept 2004, link
  46. A Design Space Exploration Scheme for Data Path Synthesis, IEEE Transactions on VLSI, pp 331-338, vol. 7, no. 3, 1999; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / PDF paper)
    1. Design Exploration With Imprecise Latency and Register Constraints, Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha, pp 2650-2662, IEEE TCAD (ICS), vol. 25, no. 12, December 2006
    2. A design framework to efficiently explore energy-delay tradeoffs, William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, pp 260--265, 9th. International Symposium on Hardware/Software Co-Design, 2001, Copenhagen, Denmark
    3. Dealing with Imprecise Timing Information in. Architectural Synthesis. Chantana Chantrapornchai, Surakumpolthorn Wanlop, SHA Edwin, X. Hu, Research report: Technical Report TR-98-5, University of Notre Dame, 1998
    4. Design Exploration Framework under Impreciseness based on Inclusion Scheduling, with W. Surakumpolthorn, E. H-M. Sha, Lecture Notes in Computer Science: Advances in Computing Science -- ASIAN'04, Chiang Mai, Thailand, 2004, pages 78-93.
    5. Presentation by Senthil Kumar Rangaswamy in the course CPE 490/590, University of Alabama in Huntsville,
  47. A Probabilistic Estimator for the Vertex Deletion Problem, Computers and Mathematics with Applications, pp 1-4, vol 35, no. 6, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / postscript paper)
  48. Complexity of Fragmentable Object Bin Packing and an Application, Computers and Mathematics with Applications, pp. 91-97, vol. 35, No.11, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / PDF paper)
    1. Handbook of approximation algorithms and metaheurististics edited by Teofilo F. González, Chapman & Hall/CRC, ISBN 1-58488-550-5
    2. Approximation schemes for packing with item fragmentation, Shachnai, H., Tamir, T., Yehezkely, O., Theory of Computing Systems 43 (1), pp. 81-98, 2008
    3. Fast asymptotic FPTAS for packing fragmentable items with costs, Shachnai, H., Yehezkely, O., Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 4639 LNCS, pp. 482-493, 2007
    4. Elastic reservations for efficient bandwidth utilization in LambdaGrids, Naiksatam, S., Figueira, S., Future Generation Computer Systems 23 (1), pp. 1-22, 2007
    5. Approximation schemes for packing with item fragmentation, Shachnai, H., Tamir, T., Yehezkely, O., Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3879 LNCS, pp. 334-347, 2006
    6. Edward G. Coffman, Jr., János Csirik, David S. Johnson, Gerhard J. Woeginger; An Introduction to Bin packing; May, 2004
    7. Nir Naaman, Raphael Rom; Packet Scheduling with Fragmentation; IEEE Infocom; 2002
    8. Nir Menakerman, Raphael Rom: Analysis of Transmissions Scheduling with Packet Fragmentation; Discrete Mathematics & Theoretical Computer Science 4 (2): 139-156 (2001)
    9. Nir Menakerman and Raphael Rom; Bin Packing with Item Fragmentation; Lecture Notes in Computer Science; Algorithms and Data Structures : 7th International Workshop, WADS 2001, Providence, RI, USA, August, 8-10, 2001, Proceedings;vol 2125, pp 313-324; 2001; F. Dehne, J.-R. Sack, R. Tamassia (Eds.); ISSN: 0302-9743
    10. Approximation Schemes for Packing with Item Fragmentation, Omer Yehezkely, Master of Science Thesis in Computer Science, Israel Institute of Technology, Haifa, November 2006
    11. Chapter 33. Variants of Classical One-Dimensional Bin Packing, Edward G Coffman, Joseph Y-T Leung, and Janos Csirik, Handbook of Approximation Algorithms and Metaheuristics, 2007, ISBN: 978-1-58488-550-4, link1, link2
    12. On-line A-shaped Bin Packing, Systems Engineering--Theory & Practice, vol 22, issue 7, 2002, link
  49. Some New Results in the Complexity of Allocation and Binding in Data Path Synthesis, Computers and Mathematics with Applications, pp 93-105, vol 35, no. 10, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / postscript paper)
    1. Platform-based resource binding using a distributed register-file microarchitecture, Jason Cong and Yiping Fan and Wei Jiang, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pp 709--715, 2006, San Jose, California
    2. A proposal of a greedy-GA combined algorithm for data transfer binding problems, Yasuhito Shikata, Nobuo Funabiki, Junji Kitamichi, Electronics and Communications in Japan (Part III: Fundamental Electronic Science), pp 13-22, vol 84, no 5, 2001
  50. Complexity of Scheduling in High Level Synthesis, VLSI DESIGN, pp 337-346, vol. 7, no. 4, 1998; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / postscript paper)
    1. An Efficient List-Based Scheduling Algorithm for High-Level-Synthesis, Sllame Azeddien M., Drábek Vladimír, EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools, Dortmund, Germany, 2002, link
  51. Allocation of registers to multiport memories based on register-interconnect optimization, Modelling and Simulation, pp. 57-64, vol. 25, no. 4, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  52. Register-Interconnect Optimization in Data Path Synthesis, Microprocessing and Microprogramming, pp. 279-288, vol. 33, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose.

Conference/Seminar Proceedings

  1. Signalling Design Automation Tool for EIs (SigDATE), Proceedings of the 65-th Annual Day Indian Railways Institute of Railway Signalling (IRISET) Secundrabad, in Gyandeep Technical Magazine, pp 49–52, Nov 24, 2022; Amit Misra, Chittaranjan Mandal, Shankhadip Mallick
  2. Traffic-Aware Consistent Flow Migration in SDN, 2020 IEEE International Conference on Communications (ICC): Next-Generation Networking and Internet Symposium, pp 1–6, 7–11 June, 2020; Ilora Maity, Sudip Misra, Chittaranjan Mandal
  3. SamaTulyataOne: A Path Based Equivalence Checker [tool paper], 12th Innovations in Software Engineering Conference, Pune, India, Feb 14-16, 2019 (ISEC 2019), Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
  4. An Equivalence Checking Framework for Array-Intensive Programs [tool paper], 15th International Symposium on Automated Technology for Verification and Analysis, Pune, India, Oct 3-6, 2017 (ATVA 2017), LNCS vol 10482, pp 84-90, Kunal Banerjee, Chittaranjan Mandal, Dipankar Sarkar
  5. SamaTulyata: An Efficient Path Based Equivalence Checking Tool [tool paper], 15th International Symposium on Automated Technology for Verification and Analysis, Pune, India, Oct 3-6, 2017 (ATVA 2017), LNCS vol 10482, pp 109-116, Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan Mandal
  6. An Early Global Routing Framework for Uniform Wire Distribution in SoCs, IEEE International System-on-Chip Conference (SOCC 2016), Seattle, Sep 6-9, 2016, Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal
  7. Formal Verification of Movement Authorities in Automatic Train Control Systems, International Conference on Railway Engineering 2016 (ICRE), Brussels, Belgium, May 12-13, 2016, Shiladitya Ghosh, Pallab Dasgupta, Chittaranjan Mandal, Alok Katiyar
  8. Translation Validation of Loop and Arithmetic Transformations in the Presence of Recurrences, Languages, Compilers, Tools and Theory for Embedded Systems, Santa Barbara, California, June 13-14, 2016 (LCTES 2016), pp 31-40 Kunal Banerjee, Chittaranjan Mandal, Dipankar Sarkar
  9. A Novel EPE Aware Hybrid Global Route Planner after Floorplanning, International Conference on VLSI Design (VLSID 2016), Montpellier, Jan 4-8, 2016, Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal
  10. Establishing Equivalence of Expressions: An Automated Evaluator Designer’s Perspective, 3rd Mining Intelligence and Knowledge Exploration (MIKE) 2015, IIIT Hyderabad, Dec 9--11, 2015, K K Sharma, Kunal Banerjee, Chittaranjan Mandal
  11. An efficient path based equivalence checking for Petri net based models of programs, 9thIndia Software Engineering Conference (ISEC) 2016, Goa, Feb 18-20, 2016, Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
  12. Layout Validation using Graph Grammar and Generation of Yard Specific Safety Properties for Railway Interlocking Verification, 22nd Asia Pacific Software Engineering Conference (APSEC) 2015, pp 330-337, New Delhi, Dec 1-4, 2015, Devleena Ghosh, Chittaranjan Mandal
  13. A Virtual Laboratory for Computer Organisation and Logic Design (COLDVL) and Its Utilisation for MOOCs, 3rd International Conference on MOOC, Innovation and Technology in Education (MITE) 2015, Amritsar, Oct 1-2, 2015, Gargi Roy, Devleena Ghosh, Chittaranjan Mandal
  14. A Benchmark Programming Assignment Suite for Quantitative Analysis of Student Performance in Early Programming Courses, 3rd International Conference on MOOC, Innovation and Technology in Education (MITE) 2015, Amritsar, Oct 1-2, 2015, K K Sharma, Kunal Banerjee, Chittaranjan Mandal
  15. Determining Equivalence of Expressions: An Automated Evaluator's Perspective, 7th International Conference on Technology for Education (T4E) 2015, Warangal, Dec 10-12, 2015, K K Sharma, Kunal Banerjee, Chittaranjan Mandal
  16. A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization, 7th International Conference on Technology for Education (T4E) 2015, Warangal, Dec 10-12, 2015, Gargi Roy, Devleena Ghosh, Chittaranjan Mandal
  17. Aiding Teaching of Logic Design and Computer Organization Through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool, 7th International Conference on Technology for Education (T4E) 2015, Warangal, Dec 10-12, 2015, Gargi Roy, Devleena Ghosh, Chittaranjan Mandal, Indraneel Mitra
  18. A Translation Validation Framework for Symbolic Value Propagation Based Equivalence Checking of FSMDAs 15th International Working Conference on Source Code Analysis and Manipulation (SCAM) 2015, Bremen, Sep 27-28, 2015, Kunal Banerjee, Chittaranjan Mandal, Dipankar Sarkar
  19. Translation Validation of Transformations of Embedded System Specifications using Equivalence Checking, ISVLSI 2015, Montpellier, July 08-10, 2015, Kunal Banerjee, Chittaranjan Mandal, Dipankar Sarkar (best PhD forum paper certificate)
  20. Validating SPARK: High Level Synthesis compiler, ISVLSI 2015, Montpellier, July 08-10, 2015, Dipankar Sarkar, Soumyadip Bandyopadhyay, Chittaranjan Mandal
  21. A New Method for Defining Monotone Staircases in VLSI Floorplans, ISVLSI 2015, Montpellier, July 08-10, 2015, Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal
  22. Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs, IEEE/ACM 37th IEEE International Conference on Software Engineering (ICSE), 2015, Florence, 16-24 May 2015, Soumyadip Bandyopadhyay, Chittaranjan Mandal, Dipankar Sarkar
  23. A Path-Based Equivalence Checking Method for Petri net based Models of Programs, ICSOFT 2015, Colmar, July 20-22, 2015, Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan Mandal
  24. Translation Validation of Transformations of Embedded System Specifications using Equivalence Checking, ISVLSI 2015, Montpellier, July 08-10, 2015, Kunal Banerjee, Chittaranjan Mandal, Dipankar Sarkar
  25. Automated Checking of the Violation of Precedence of Conditions in else-if Constructs in Students' Programs, IEEE MITE 2014, Patiala, Dec 19-20, 2014, K K Sharma, Indra Vikas, Kunal Banerjee, Chittaranjan Mandal
  26. A Scheme for Automated Evaluation of Programming Assignments using FSMD based Equivalence Checking, Proceedings of IBM I-CARE 2014, IISC-Bangalore, Oct 09-11, 2014, K K Sharma, Kunal Banerjee, Chittaranjan Mandal
  27. Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks, Proceedings of 17th Euromicro Conference on Digital System Design (DSD), Verona, Italy, pp 520-527, August 27-29, 2014, Partha De, Kunal Banerjee, Chittaranjan Mandal, Debdeep Mukhopadhyay
  28. A BDD based Secure Hardware Design Method to Guard Against Power Analysis Attacks, Proc. of the 18th VLSI Design & Test Symposium (VDAT), Coimbatore, India, July 16-18, 2014, Partha De, Kunal Banerjee, Chittaranjan Mandal.
  29. Extending the Scope of Translation Validation by Augmenting Path Based Equivalence Checkers with SMT Solvers, Proc. of the 18th VLSI Design & Test Symposium (VDAT), Coimbatore, India, July 16-18, 2014, Kunal Banerjee, Chittaranjan Mandal, D Sarkar.
  30. A Distributed Greedy Algorithm for Construction of Minimum Connected Dominating Set in Wireless Sensor Network, Proceedings of Applications and Innovations in Mobile Computing (AIMoC 2014), Calcutta, India, pp 104-110, Feb 27-Mar 01, 2014, Jasaswi Prasad Mohanty, Chittaranjan Mandal
  31. Global Routing using Monotone Staircases with Minimal Bends, Proceedings of 27th IEEE International Conference on VLSI Design, IIT Bombay, India, pp 369-374, January 5-9, 2014, Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal
  32. Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results, Proceedings of 19th International Conference on Management of Data (COMAD 2013), Ahmedabad, Dec 19-31, 2013, Ariyam Das, Chittaranjan Mandal, Chris Reade
  33. STAIRoute: Global Routing using Monotone Staircase Channels, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2013, Natal, Brazil, pp 90--95, Aug 5-7, 2013, Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal
  34. Re-using Refresh for Self-testing DRAMs, Proceedings of ISED 2013, NTU, Singapore, 12-13 December 2013, Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta
  35. Experimentation with SMT Solvers and Theorem Provers for Verification of Loop and Arithmetic Transformations, Proceedings of IBM I-CARE 2013, IIT Delhi, Oct 17-19, 2013, Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal (best paper award)
  36. Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic, Proceedings of 16th Euromicro Conference on Digital System Design (DSD), Santander, Joaquín Costa, Spain, September 4-6, 2013, Partha De, Kunal Banerjee, Chittaranjan Mandal, Debdeep Mukhopadhyay
  37. Verification of KPN level transformation, Proceedings of 26th IEEE International Conference on VLSI Design, Hyatt Regency, Pune, India, pp 338-343, January 5-10, 2013, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
  38. A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques, Proceedings of the IEEE International Symposium on System Design (ISED) 2012, Bengal Engineering and Science University, Shibpur, India; pp 67-71, December 19-22, 2012, Kunal Banerjee, Chandan Karfa, Dipankar Sarkar and Chittaranjan Mandal
  39. Workload Driven Power Domain Partitioning, Proceedings of the 16th International Symposium on VLSI Design and Test Bengal Engineering and Science University, Shibpur, India; July 1-4, 2012, Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta and Chittaranjan Mandal
  40. A Faster Hierarchical Balanced bipartitioner for VLSI Floor-plans using Monotone Staircase Cuts, Proceedings of the 16th International Symposium on VLSI Design and Test Bengal Engineering and Science University, Shibpur, India; July 1-4, 2012, Bapi Kar, Susmita Sur-Kolay, Sridhar H Rangarajan and Chittaranjan Mandal
  41. Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker, Proceedings of the 16th International Symposium on VLSI Design and Test Bengal Engineering and Science University, Shibpur, India; July 1-4, 2012, Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar and Chittaranjan Mandal
  42. POWER-SIM: An SOC Simulator for Estimating Power Profiles of Mobile Workloads, Proceedings of IEEE International Symposium on Electronic System Design (ISED) 2011, Kochi, India, pp 273-278, Dec 19-21, 2011, Priyankar Ghosh, Aritra Hazra, Niraj Bhilegaonkar, Pallab Dasgupta, Chittaranjan Mandal
  43. Equivalence Checking of Array-Intensive Programs, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011, Chennai, India, pp 156-161, July 4-6, 2011, Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal (Abstract/PDF paper)
  44. Verification of Register Transfer Level Low Power Transformations, Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2011, Chennai, India, pp 313-314, July 4-6, 2011, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal (Abstract/PDF paper)
  45. An Improved Greedy Construction of Minimum Connected Dominating Sets in Wireless Networks, Proceedings of 2011 IEEE Wireless Communications and Networking Conference 2011 (IEEE WCNC 2011 - Network), Cancun, Mexico, pp 1601-1606, March 28-31, 2011, Ariyam Das, Chittaranjan Mandal, Chris Reade, M Aasawat (slides)
  46. Design and Implementation of Packet Filter Firewall using Binary Decision Diagram, Proceedings of 2011 IEEE Student's Technology Symposium (TechSym), IIT Kharagur, India, Jan 14-16, 2011, G Paul, A Pothnal, C Mandal, B B Bhattacharya (Abstract)
  47. Data-flow Driven Equivalence Checking for Verification of Code Motion Techniques, Proceedings of IEEE ISVLSI 2010, Lixouri Kefalonia, Greece, pp 428-433, July 5-7, 2010, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
  48. A BDD-based Design of an Area-Power Efficient Asynchronous Adder, Proceedings of IEEE ISVLSI 2010, Lixouri Kefalonia, Greece, pp 29-34, July 5-7, 2010, Gopal Paul, Rohit Reddy, Chittaranjan Mandal, Bhargab B. Bhattacharya (Photos of SCA resistant and MEDB adders)
  49. A Methodology for Sizing of Analog High-Level Topologies using Computational Intelligence Techniques, International Conference on Emerging Trends in Engineering Technologies (ICETES 2010), Kanyakumari, pp 520-523, March 25-26, 2010, Soumya Pandit, Chittaranjan Mandal, Amit Patra (best paper award)
  50. Location Updates of Mobile Node in Wireless Sensor Networks, Proceedings of the 5th International Conference on Mobile Ad-hoc and Sensor Networks, 2009. (MSN '09) Fujian, pp 311--318, 14-16 Dec. 2009, Rajiv Misra, Chittaranjan Mandal
  51. Efficient location updates of mobile node in wireless sensor networks, Proceedings of TENCON 2009 - 2009 IEEE Region 10 Conference Singapore, pp 1--6, 23--26 Jan. 2009, Rajiv Misra, Chittaranjan Mandal
  52. MMS: Multi Merge and Split Buffer Management Scheme for Video-on-Demand Systems, Proceedings of 3rd International IEEE Conference on Internet Multimedia Systems Architecture and Applications (IMSAA 09), Hotel Radha Regent, Bangalore, India, pp 1-6, December 9-11, 2009, Anant V Nimkar, Chittaranjan Mandal, Chris Reade (PDF paper)
  53. Video Placement and Disk Load Balancing Algorithm for VoD Proxy Server, Proceedings of 3rd International IEEE Conference on Internet Multimedia Systems Architecture and Applications (IMSAA 09), Hotel Radha Regent, Bangalore, India, pp 1-6, December 9-11, 2009, Anant V Nimkar, Chittaranjan Mandal, Chris Reade (PDF paper)
    1. A. Vinay, K. G. Abhijit, M. Saifulla, D. Jayashree, and T. N. Anitha. 2011. A comparative analysis of centralized and distributed dynamic load balancing algorithms for cluster based video-on-demand systems. In Proceedings of the International Conference & Workshop on Emerging Trends in Technology (ICWET '11). ACM, New York, NY, USA, 351-356. link
  54. Systematic Methodology for High-Level Performance Modeling of Analog Systems, Proceedings of 22nd IEEE International Conference on VLSI Design Taj Palace Hotel, New Delhi, India, pp 361-366, January 5-9, 2009, Soumya Pandit, Chittaranjan Mandal, Amit Patra (Abstract / PDF paper)
    1. Optimal specification of a receiver blocks from global specifications: Example of IEEE 802.15. 4Optimal specification of a receiver blocks from global specifications: Example of IEEE 802.15. 4Optimal specification of a receiver blocks from global specifications: Example of IEEE 802.15. 4, Ndungidi, P. and Dongmo, U. and Dualibe, F. and Valderrama, C. link
  55. A novel approach for the identification of totally symmetric Boolean functions in the application of efficient system design, Third IEEE International Design and Test Workshop, 2008. (IDT 2008), El Habib Hotel, Monastir, pp.243-248, 20-22 Dec. 2008, Gopal Paul, Ashish Tiwari, Ajit Pal, C R Mandal, (PDF paper)
  56. Low power design of on-line testers for digital circuits using state encoding, Third IEEE International Design and Test Workshop, 2008. (IDT 2008), El Habib Hotel, Monastir, pp.142-147, 20-22 Dec. 2008, Gopal Paul, Santosh Biswas, Ajit Pal, C R Mandal, (PDF paper)
  57. Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells, Third IEEE International Design and Test Workshop, 2008. (IDT 2008), El Habib Hotel, Monastir, pp.123-128, 20-22 Dec. 2008, Gopal Paul, Rohit Reddy, Jyotirmoy Ghosh, Ajit Pal C R Mandal; Bhargab B Bhattacharya (PDF paper)
  58. Verification of Data-path and Controller Generation Phase of High-level Synthesis, Proceedings of 15th International IEEE Conference on Advanced Computing & Communication (ADCOM 2007) IIT Guwahati, India, pp 315-320, December 18-21, 2007, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal (Abstract / PDF paper / award)
  59. Automatic Detection of Human Fall in Video, Proceedings of Second International Conference on Pattern Recognition and Machine Intelligence (PReMI'07), Calcutta, India, pp 616--623, December 18-22, 2007, Vinay Vishwakarma, Chittaranjan Mandal, Shamik Sural (Abstract)
    1. Fall detection and activity recognition with machine learning Luštrek, B Kaluža - Informatica, 2009 link
    2. How to detect human fall in video? An overview, J Willems, et. al. link
  60. Hand-in-hand verification of high-level synthesis, Proceedings of IEEE 17th great lakes symposium on Great lakes symposium on VLSI (GLSVLSI'07) Stresa-Lago Maggiore, Italy, pp 429--434, March 11-13, 2007, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Chris Reade (Abstract / PDF paper)
    1. Thomas Steininger, Automated Assertion Transformation Across Multiple Abstraction Levels, PhD thesis, 2009, Fakultat fur Elektrotechnik und Informationstechnik, Lehrstuhl fur Entwurfsautomatisierung
    2. Youngsik Kim , Nazanin Mansouri, Automated formal verification of scheduling with speculative code motions, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA, link
  61. Register Sharing Verification During Data-path Synthesis, Proceedings of IEEE International Conference on Computing, Theory and Applications (ICCTA'07), Calcutta, India, pp 135-140, March 5-7, 2007, C Karfa, C Mandal, D Sarkar, Chris Reade. (Abstract / PDF paper)
  62. Coordinator Rotation via Domatic Partition in Self-Organizing Sensor Networks, Proceedings of the International Symposium of Wireless Pervasive Computing 2007, San Juan, Puerto Rico, 6 pages, February 5-7, 2007, Rajiv Misra, Chittaranjan Mandal, Ratan Guha
  63. A Scheme for Recipient Specific Yet Anonymous and Transferable Electronic Cash Proc. of WEBIST 2007 Barcelona, Spain, Setúbal, pp 204-209, March 3-6, 2007, Chittaranjan Mandal, Chris Reade, (Abstract / PDF paper)
  64. ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks, 2nd International Conference on Communication Systems Software and Middleware (COMSWARE 2007), Bangalore, 7 pages, 7-12 January, 2007, Rajiv Misra, Chittaranjan Mandal (Abstract / slides) (award - certificate, jpg)
    1. High Performance Sleep-Wake Sensor Systems Based on Cyclic Cellular Automata, Y. M. Baryshnikov, E. G. Coffman, K. J. Kwak, Proceedings of the 7th international conference on Information processing in sensor networks, pp 517-526, 2008 link
    2. An Energy-Driven Adaptive Cluster Head Rotation Algorithm for Wireless Sensor Networks; Huang He-qing; Shen Jie; Yao Dao-yuan; Ma Kui; Liu Hai-tao; Journal of Electronics & Information Technology, 2009, vol 31, no 5, pp 1040-1044, ISSN: 1009-5896, CN: 11-4494/TN
  65. A Formal Approach for High Level Synthesis of Linear Analog Systems, Proceedings of ACM/IEEE GLSVLSI 2006, Philadelphia, USA, pp 345-348, April 30 -- May 2, 2006, Soumya Pandit, Chittaranjan Mandal, Amit Patra (Abstract / PDF paper)
  66. Asynchronous Design Methodology for an Efficient Implementation of Low Power ALU Proceedings of IEEE APCCAS2006, Singapore, pp 590-593, 4-7 Dec, 2006, Manikandan P, Liu B D, Chiou L Y, Sundar G, Mandal C R (Abstract / PDF paper) (award)
  67. A Hybrid Search Procedure for System-Level Analog Design Space Exploration used in High Level Synthesis of Analog Systems. (CIS-23) Proceedings of IEEE CODEC-06, Hyatt Regency, Saltlake, 18-20 Dec, 2006, Soumya Pandit, C R Mandal, Amit Patra
  68. A Formal Verification Method of Scheduling in High-level Synthesis, Proceedings of ACM/IEEE 7th International Symposium on Quality Electronic Design (ISQED 2006), San Jose, USA, pp 71-78, March 27-29, 2006, Chandan Karfa, Chittaranjan Mandal, Dipankar Sarkar, Satyam R Pentakota, Chris Reade, ISBN: 0-7695-2523-7. (Abstract / PDF paper/ slides)
    1. Thanyapat Sakunkonchak, Takeshi Matsumoto, Hiroshi Saito, Satoshi Komatsu, Masahiro Fujita, Equivalence checking in C-based system-level design by sequentializing concurrent behaviors, Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology, pp 36-42, April 02-04, 2007, Phuket, Thailand, link
    2. Kousuke Mijaji, Study on Applications of Room-Temperature Operating. Silicon Single-Electron Transistors, PhD thesis, 2007, Univerisity of Tokyo
    3. Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita, Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph, Journal of Universal Computer Science, vol. 13, no. 13, pp 1972-2001, 2007, link
    4. Bijan Alizadeh and Masahiro Fujita, Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram, CSICC 2008, CCIS 6, pp. 697­704, 2008, link
    5. Bijan Alizadeh and Masahiro Fujita, A Hybrid Approach for Equivalence Checking Between System Level and RTL Descriptions, IWLS07, USA, pp. 298-304, 2007, link
    6. B. Alizadeh, M. Fujita, Automatic Merge-point Detection for Sequential Equivalence Checking of System-level and RTL Descriptions, ATVA07, Japan, pp. 129-144, 2007, link
    7. Sudipta Kundu, Sorin Lerner, and Rajesh Gupta, Validating High-Level Synthesis, Proceedings of the 2008 International Conference on Computer-Aided Verification (CAV), pp 459-472, 2008, link
    8. Sudipta Kundu, Sorin Lerner and Rajesh Gupta, High-Level Verification, IPSJ Transactions on Systems LSI Design Methodology, vol 2, pp 131-144, August, 2009
    9. Lars Gesellensetter, Sabine Glesner, and Elke Salecker, Formal Verification with Isabelle/HOL in Practice: Finding a Bug in the GCC Scheduler, FMICS 2007, pp 85-100, link
    10. Tsung-Hsi Chiang and Lan-Rong Dung, Verification of Dataflow Scheduling, International Journal of Software Engineering and Knowledge Engineering and Knowledge Engineering Vol. 18, no. 6, pp 737-758, 2008, link
    11. Tsung-Hsi Chiang, Lan-Rong Dung, Verification method of dataflow algorithms in high-level synthesis, Journal of Systems and Software, v.80 n.8, p.1256-1270, August, 2007, link
  69. Ant-aggregation: Ant Colony Algorithm for optimal data aggregation in Wireless Sensor Networks, Proceedings of the Third IEEE and IFIP International Conference on Wireless and Optical Communications Networks (WOCN 2006), Le Meridien, Bangalore, India, Apr 11-13, 2006, Rajiv Misra, Chittaranjan Mandal (Abstract / PDF paper)
    1. Data aggregation in wireless sensor networks using ant colony algorithm, Wen-Hwa Liao, Yucheng Kao, Chien-Ming Fan, Journal of Network and Computer Applications, pp 387-401, vol 31, no 4, Nov 2008, link
    2. Introducing an ACO Based Paradigm for Detecting Wildfires using Wireless Sensor Networks, R Chandrasekar, Sudip Misra, International Symposium on Ad Hoc and Ubiquitous Computing, 2006. (ISAUHC '06), pp 112-117, 20-23 Dec 2006, link
    3. Probabilistic Ant based Clustering for Distributed Databases, Chandrasekar, R.; Vijaykumar, V.; Srinivasan, T., 3rd International IEEE Conference on Intelligent Systems, Sept. 2006, pp 538-545 link
    4. An Ant Odor Analysis Approach to the Ant Colony Optimization Algorithm for Data-Aggregation, Vijaykumar, V.; Chandrasekar, R.; Srinivasan, T., International Conference on Wireless Sensor Networks, Wireless Communications, Networking and Mobile Computing (WiCOM 2006), pp.1-4, 22-24 Sept. 2006, link
    5. A probabilistic zonal approach for swarm-inspired wildfire detection using sensor networks, Chandrasekar Ramachandran, Sudip Misra, Mohammad S. Obaidat, International Journal of Communication Systems, vol 21, no 10, 2006, pp 1047-1073, link
  70. Animating Algorithms over the Web Proc. of WEBIST 2006, Setúbal, Portugal, pp 403-407, Apr 11-13, 2006, Chittaranjan Mandal, Chris Reade, ISBN 978-9728865-47-4. (Abstract / PDF paper)
  71. A System for Automatic Evaluation of Programs for Correctness and Performance Proc. of WEBIST 2006, Setúbal, Portugal, pp 196-203, Apr 11-13, 2006, Amit Kumar Mandal, Chittaranjan Mandal, Chris Reade, ISBN 978-9728865-47-4. (Abstract / PDF paper)
  72. Verification of Scheduling in High-level Synthesis, Proceedings of IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, pp 141-146, Mar 2-3, 2006, Chandan Karfa, S R Pentakota, Chittaranjan Mandal, Dipankar Sarkar, Chris Reade. (Abstract / PDF paper)
  73. A Technique for Algorithm Animation Over the Web, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 163-166, Feb 10-11, 2006, Chittaranjan Mandal, Chris Reade. (Abstract / PDF paper)
  74. High-level Synthesis of Linear Analog Systems, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 389-392, Feb 10-11, 2006, Soumya Pandit, Chittaranjan Mandal, Amit Patra. (Abstract / PDF paper / slides)
  75. An Efficient Algorithm for scheduling verification, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 397-400, Feb 10-11, 2006, Chandan Karfa, S R Pentakota, Chittaranjan Mandal, Dipankar Sarkar, Chris Reade. (Abstract / PDF paper)
  76. Design and Implementation of an Automatic Program Evaluation System, Proc. of International Conference on Emerging Applications of IT, Elsevier, Science City, Calcutta, pp 325-328, Feb 10-11, 2006, Amit Mandal, Chittaranjan Mandal, Chris Reade. (Abstract / PDF paper)
  77. High Level Synthesis of Higher Order Continuous Time State Variable Filter with Minimum Sensitivity and Hardware Count, Proceedings of DATE 06, ICM, Munich, Germany, pp 1203-1204, Mar 6-10, 2006, Soumya Pandit, Chittaranjan Mandal, Amit Patra. (Abstract / PDF paper)
  78. Optimal Clustering in Sensor Networks Using Game-theoretic Particle Swarm Optimization, Proc. of the 4th Asian International Mobile Computing Conference (AMOC 2006), Hyatt Regency, Calcutta, India, pp 114-118, Jan 4-7, 2006, Rajiv Misra, Chittaranjan Mandal, ISBN: 0-07-060834-2. (Abstract / PDF paper)
  79. An Improved Energy Efficient Distributed Clustering Algorithm for Large Wireless Sensor Networks, Proc. of the 4th Asian International Mobile Computing Conference (AMOC 2006), Hyatt Regency, Calcutta, India, pp 95-104, Jan 4-7, 2006, Rajiv Misra, Chittaranjan Mandal, ISBN: 0-07-060834-2. (Abstract / PDF paper)
  80. Self-Healing for Self-Organizing Cluster Sensor Networks, Proc. of IEEE 2006 Annual India Conference (INDICON 2006), India Habitat Centre, New Delhi, India, Sept 15-17, 2006, Rajiv Misra, Chittaranjan Mandal
    1. Network Reconfiguration for Energy Efficient Clustering of Wireless Sensor Networks, Dujdow Buranapanichkit, Ekavic Chanpen, Proceedings of the 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2008, link
  81. SAST: An Interconnection Aware High-Level Synthesis Tool, Proc. of the 9th VLSI Design & Test Symposium (VDAT), Bangalore, India, pp 285-293, August 11-13, 2005, C R Mandal, D Sarkar, C Karfa, J S Reddy, S Biswas. (Abstract / PDF paper / Slides)
  82. Performance comparison of AODV/DSR on-demand routing protocols for ad hoc networks in constrained situation, Proceedings of IEEE International Conference on Personal Wireless Communications, 2005 (ICPWC 2005), New Delhi, India, pp 86-89, January 23-25, 2005, Misra, R., Mandal, C.R. (Abstract / PDF paper)
    1. Jaime Lloret, Miguel Garcia and Jesus Tomas, Improving Mobile and Ad-hoc Networks performance using Group-Based Topologies, Wireless Sensor and Actor Networks II, pp 209-220, 2008, ISBN: 978-0-387-09440-3 link
    2. Muhmmad Ijaz, TCP performance evaluation in MANET, MSc in Electrical Engineering, Blekinge Instute of Technology, March 2009 link
  83. A Web-based Automatic Evaluation System, Proc. of the 3rd European Conference on eLearning, Paris, France, pp 189-196, 25-26 November 2004, C Mandal, V L Sinha, C M P Reade. (Abstract / Extended abstract / PDF paper / presentation slides)
  84. A New Approach to Timing Analysis using Event Propagation and Temporal Logic, Proceedings of DATE '04, Paris, France, pp 1198 - 1203, 2004, Arijit Mondal, Partha P Chakrabarti, C Mandal. (Abstract / PDF paper)
  85. A Web-Based Course Management Tool, Proc. of the 2nd European Conference on e-Learning, Nov 6-7, Glasgow, UK, pp 293-302, 2003, C. Mandal, V. L. Sinha, C. M. P. Reade. (Abstract / PDF paper)
  86. Timing Analysis of Tree-like RLC Circuits, Proceedings of IEEE International Symposium on Circuits and Systems, Scottsdale, Arizona, USA, pp. 838-841, 2002, Rajendran, B., Kheterpal, V., Das, A., Majumder, J., Mandal, C., Chakrabarti, P.P. (Abstract / PDF paper)
  87. A Genetic Algorithm for the Synthesis of Structured Data Paths, Proceedings of IEEE International Conference on VLSI Design 2000, Calcutta, INDIA, pp. 206-211, 2000; C. Mandal, R. M. Zimmer. (Abstract / PDF paper)
    1. Nikolaos G. Bourbakis , M. Mortazavi, A VLSI DESIGN DESIGN-SYNTHESIS METHODOLOGY AT THE TRANSISTOR LAYOUT LEVEL, Journal of Integrated Design & Process Science, v.9 n.3, p.63-85, July 2005, link
    2. Nikolaos G. Bourbakis, A generic, formal language-based methodology for hierarchical floorplanning-placement, Computer Languages, Systems and Structures, v.34 n.1, p.25-42, April, 2008, link
  88. Integrated Scheduling and Allocation for Synthesis of Structured Data Paths, Proceedings of IEEE VLSI Design & Test Workshops, August 6-7, 1998, The Habitat World, Lodi Road, New Delhi, India, on-line proceedings; C. Mandal, R. Zimmer. (Abstract)
  89. High-Level Synthesis of Structured Data Paths, Proc. of IFIP TC10 WG 10.5 International Conference on Computer Hardware Description Languages and Their Applications, 20-25 April 1997, Toledo, Spain; pp. 92-94; C. A. Mandal, R. M. Zimmer. (Extended version available) (Abstract / postscript paper)
  90. Design Space Exploration for Data Path Synthesis, Proceedings of 10th IEEE International Conference on VLSI Design '97, Hydrabad, INDIA, pp. 166-173, 1997; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / PDF paper)
    1. Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints, Chantrapornchai Chantana, Surakumpolthorn Wanlop, SHA Edwin pp 259-270, Embedded and ubiquitous computing, 2004, link
  91. Allocation and Binding in Data Path Synthesis Using a Genetic Approach, Proceedings of the 9th International Conference on VLSI Design, Bangalore, INDIA, 3-6 January, pp. 122-125, 1996; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / PDF paper)
    1. An Indexed Bibliography of Genetic Algorithms in Electronics and VLSI Design and Testing, A. Jarmo, 1994, link
  92. Port Assignment for Dual and Triple Port Memories Using a Genetic Approach, Proceedings of IFIP Asia/Pacific Conference on Hardware Description Languages, Bangalore, INDIA, pp. 60-64, 1996; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (Abstract / postscript paper)
  93. Use of Multi-Port Memories in Programmable Structures for Architectural Synthesis, Proceedings of the Eighth Annual IEEE International Conference on Innovative Systems in Silicon, Austin, 9-11 October, pp. 341-351, 1996; C. A. Mandal, R. M. Zimmer. (PDF paper)
  94. Allocation of Registers to Multi-port Memories Based on Register--Interconnect Optimization, Proceedings of ICAUTO -International Conference- 1995, Indore, pp. 611-614, 1995; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  95. A Framework for High Level Synthesis, International Workshop on Artificial Intelligence, I.I.M., Calcutta, March, 1994; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  96. Complexity of Scheduling 2-Operation Chains and Some Other Related Scheduling Problems, Proceedings of the Fourth National Seminar on Theoretical Computer Science, IIT Kanpur, INDIA, pp. 171-180, 1994; C. A. Mandal, P. P. Chakrabarti, S. Ghose.
  97. Interconnect Optimization Techniques in Data Path Synthesis, Proceedings of 4th IEEE International Conference on VLSI Design '92, Bangalore, pp. 85-90, 1991; C. A. Mandal, P. P. Chakrabarti, S. Ghose. (PDF paper)
  98. ABS: An Automated Behavioural Synthesis System, Proceedings of VLSI Design '90, Bangalore, pp. 18-23, 1990; C. A. Mandal, P. Pal Chaudhuri.

 
  dblp, h-index)

Workshops

  1. Workshop on Railway Signalling Automation using (SigDATE), conducted through CEP (IIT/CEP/WOR/WOR/2023-2024/CS/178) at IIT Kharagpur, Apr 22-23, Apr 25-26, Apr 29-30, May 2-3, May 6-7, 2024; Chittaranjan Mandal
  2. Workshop on Railway Signalling Automation for Indian Railway Signalling Engineers towards adoption of developed signal Interlocking tool for SIP capture and RCC generation (SigDATE), conducted through CEP (IIT/CEP/WOR/WOR/2022-2023/CS/61 ) at IIT Kharagpur, Aug 4-5, Aug 22-23, Aug 25-26, 2022; Chittaranjan Mandal
  3. Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers, IMPECS-POPL Workshop on Emerging Research and Development Trends in Programming Languages (WEPL), Bombay (Mumbai), Jan 18, 2015; Kunal Banerjee, Chittaranjan Mandal and Dipankar Sarkar
  4. Translation Validation using Path-Based Equivalence Checking of Petri net based Models of Programs, IMPECS-POPL Workshop on Emerging Research and Development Trends in Programming Languages (WEPL), Bombay (Mumbai), Jan 18, 2015; Soumyadip Bandyopadhyay, Dipankar Sarkar and Chittaranjan Mandal

Books

  1. Soumya Pandit, Chittaranjan Mandal, Amit Patra, Nano-scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design, CRC Press, December 2013, (ISBN 978-1-4665-6426-8, nanoGift).
  2. Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking, LAMBERT Academic Publishing, August 2010 (ISBN 978-3-8383-9813-6).

Book Chapters

  1. Sukriti Dhang, P K Jana and Chittaranjan Mandal, A virtual laboratory for basic electronics, in Journal of Engineering, Science and Management Education, volume-10 (1), pp 67-74, NITTTR, Bhopal, 2017 (ISSN: 0976-0121)
  2. J P Mohanty, Chittaranjan Mandal, Connected Dominating Set in Wireless Sensor Network, in Handbook of Research on Advanced Wireless Sensor Network Applications, Protocols, and Architectures, IGI Global, Aug 2016 (ISBN: 1522504869)
  3. Ariyam Das, Chittaranjan Mandal and Chris Reade, A Survey of CDS Construction Techniques for Ad hoc Sensor Networks, in Wireless Sensor Networks From Theory to Applications, pp 247-264, Ibrahiem M M El Emary and S Ramakrishnan (Eds.), CRC Press, Aug 2013 (ISBN: 978-1-4665-1810-0)
  4. Vinay Viswakarma, Shamik Sural and Chittaranjan Mandal, Fall Detection from a Video in the Presence of Multiple Persons, in Machine Interpretation of Patterns: Image Analysis and Data Mining, R. K. De, D. P. Mandal and A. Ghosh (Eds.), Chapter 9, pp 167-193, World Scientific Press, Jan 2010, (ISBN: 978-981-4299-18-3).
  5. Mandal, A., Mandal, C., Reade, C. (2009), Interface and Features for an Automatic 'C' Program Evaluation System, in Solutions and Innovations in Web-Based Technologies for Augmented Learning: Improved Platforms, Tools and Applications by Nikos Karacapilidis (Ed.), Chapter X, pp. 168-185, IGI Global, Feb 2009 (ISBN: 978-1-60566-238-1).
  6. Mandal, A, Mandal, C, Reade, C, A System for Automatic Evaluation of Programs for Correctness and Performance, in J. Filipe, J. Cordeiro, and V. Pedrosa (Eds.), Web Information Systems and Technologies I, pp. 367-380, Lecture Notes in Business Information Processing (LNBIP), Springer-Verlag, Berlin-Heidelberg, Mar 2007 (ISBN: 978-3-540-74062-9)

Patents

  1. System for Design of Route Control Chart and Application Logic for Interlocked Signalling, Shankhadip Mallick, Manoja RA, Chittaranjan Mandal and Amit Misra, patent application no. 202431029893, filed on Apr 12, 2024
  2. Computing system for running computationally intensive software application in computing device having limited computational resource, Lahoria Rahul and Mandal Chittaranjan, patent no. IN201400832I2, filed on 2014-08-07, published on 2016-08-26

Notes

  1. Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal, Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model, ArXiv, 2018, abs/1810.12789.
  2. Chittaranjan Mandal, Advanced System Architecture CAD [Part II]: System on Chip, prepared as learning material for the Special Manpower Development Program for Ministry of Information Technology, India, September 2004.

PhD Thesis

Complexity Analysis and Algorithms for Data Path Synthesis

Selected Student Theses

Tools

Documentation, software for Virtual laboratory for Computer Organisation and Logic Design

A Structured Architecture Synthesis Tool and Data Path Verifier (VLSI Design 2009 EDA Contest participation and VLSI Design 2009 EDA Contest award for SAST (Prize value: Rs 20,000))

Binaries (i586) and examples for value propagation based equivalence checking

Binaries (i586) and examples for assorted formal equivalence checking programs

Binaries (i586) and examples for assorted formal equivalence checking programs using Petri Net models

TCL for collaborative cover heuristic

Tool for Modelling and Validation of Interlocking for Railway Signalling Systems along with a demonstration