A survey on connected dominating set construction algorithm for wireless
sensor networks; Zhuo Liu, Bingwen Wang and Lejiang Guo; Information
Technology Journal 9 (6): 1081-1092, 2010 ISSN 1812-5638
Ant colony optimization applied to minimum weight dominating set problem,
Jovanovic Raka and Tuba Milan and Simian Dana in ACMOS'10, 2010,
link
A Survey on Connected Dominating Set Construction Algorithm for Wireless
Sensor Networks, Liu, Z. and Wang, B. and Guo, L., Information Technology
Journal, v9, n6, pp 1081--1092, 2010, issn 1812-5638
An Improved Greedy Construction of Minimum Connected Dominating Sets in
Wireless Networks, Das, A. and Mandal, C. and Reade, C. and Aasawat, M.,
IEEE WCNC 2011, pp 1601-1606, Cancun, March 28-31, 2011
Efficient Broadcasting in Multi-hop Wireless Networks with a
Realistic Physical Layer,
Wong, G.K.W. and Liu, H. and Chu, X. and Leung, Y.W. and Xie, C. in
Ad Hoc Networks, pp 1570-8705, 2010, Elsevier,
link
Building (1− ε) Dominating Sets Partition as Backbones in Wireless Sensor Networks Using Distributed Graph Coloring,
D Mahjoub, D Matula - Distributed Computing in Sensor Systems, 2010 - Springer
link
VBS: maximum lifetime sleep scheduling for wireless sensor networks using
virtual backbones, Y Zhao, J Wu, F Li, S Lu - INFOCOM, 2010 Proceedings IEEE, 2010
link
An Improved Greedy Construction of Minimum Connected Dominating Sets in
Wireless Networks, Das, A. and Mandal, C. and Reade, C. and Aasawat, M.,
IEEE WCNC 2011, pp 1601-1606, Cancun, March 28-31, 2011
Building (1− ε) Dominating Sets Partition as Backbones in Wireless Sensor Networks Using Distributed Graph Coloring,
D Mahjoub, D Matula - Distributed Computing in Sensor Systems, 2010 - Springer
link
Base Station Positioning and Relocation in Wireless Sensor Networks,
P Dehleh Hossein Zadeh - repository.library.ualberta.ca,
link
Xuejun Tan , Bir Bhanu, Fingerprint matching by genetic algorithms, Pattern
Recognition, v.39 n.3, p.465-477, March, 2006
An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis
Harmanani H, Saliba Rony,
Journal of Circuits, Systems, and Computers, World Scientific Publishing, vol 14,
no 2, pp 347-366, April 2005
Scheduling and allocation using closeness tables,
Burns, F. Shang, D. Koelmans, A. Yakovlev, A.,
Proceedings of the IEE, Computers and Digital Techniques,
pp 332-340, vol 151, issue 5, Sept 2004,
link
Design Exploration With Imprecise Latency and Register Constraints,
Chantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha,
pp 2650-2662, IEEE TCAD (ICS), vol. 25, no. 12, December 2006
A design framework to efficiently explore energy-delay tradeoffs,
William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria,
pp 260--265,
9th. International Symposium on Hardware/Software Co-Design, 2001,
Copenhagen, Denmark
Dealing with Imprecise Timing Information in. Architectural Synthesis. Chantana
Chantrapornchai, Surakumpolthorn Wanlop, SHA Edwin, X. Hu, Research report:
Technical Report TR-98-5, University of Notre Dame, 1998
Design Exploration Framework under Impreciseness based on Inclusion Scheduling,
with W. Surakumpolthorn, E. H-M. Sha, Lecture Notes in Computer Science: Advances
in Computing Science -- ASIAN'04, Chiang Mai, Thailand, 2004, pages 78-93.
Presentation by Senthil Kumar Rangaswamy in the course CPE 490/590, University of
Alabama in Huntsville,
Handbook of approximation algorithms and metaheurististics
edited by Teofilo F. González, Chapman & Hall/CRC, ISBN 1-58488-550-5
Approximation schemes for packing with item fragmentation, Shachnai, H.,
Tamir, T., Yehezkely, O., Theory of Computing Systems 43 (1), pp. 81-98, 2008
Fast asymptotic FPTAS for packing fragmentable items with costs, Shachnai,
H., Yehezkely, O., Lecture Notes in Computer Science (including subseries Lecture
Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 4639 LNCS,
pp. 482-493, 2007
Elastic reservations for efficient bandwidth utilization in LambdaGrids,
Naiksatam, S., Figueira, S., Future Generation Computer Systems 23 (1), pp. 1-22,
2007
Approximation schemes for packing with item fragmentation, Shachnai, H.,
Tamir, T., Yehezkely, O., Lecture Notes in Computer Science (including subseries
Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3879
LNCS, pp. 334-347, 2006
Nir Menakerman, Raphael Rom: Analysis of Transmissions Scheduling with
Packet Fragmentation; Discrete Mathematics & Theoretical Computer Science
4(2): 139-156 (2001)
Nir Menakerman and Raphael Rom; Bin Packing with Item Fragmentation;
Lecture Notes in Computer Science; Algorithms and Data
Structures : 7th
International Workshop, WADS 2001, Providence, RI, USA, August, 8-10, 2001,
Proceedings;vol 2125, pp 313-324; 2001; F. Dehne, J.-R. Sack, R. Tamassia (Eds.);
ISSN: 0302-9743
Approximation Schemes for Packing with Item Fragmentation,
Omer Yehezkely, Master of Science Thesis in Computer Science,
Israel Institute of Technology, Haifa, November 2006
Chapter 33. Variants of Classical One-Dimensional Bin Packing,
Edward G Coffman, Joseph Y-T Leung, and Janos Csirik,
Handbook of Approximation Algorithms and Metaheuristics, 2007,
ISBN: 978-1-58488-550-4,
link1,
link2
On-line A-shaped Bin Packing,
Systems Engineering--Theory & Practice, vol 22, issue 7, 2002,
link
Platform-based resource binding using a distributed register-file microarchitecture,
Jason Cong and Yiping Fan and Wei Jiang,
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided
design,
pp 709--715, 2006,
San Jose, California
A proposal of a greedy-GA combined algorithm for data transfer binding problems,
Yasuhito Shikata, Nobuo Funabiki, Junji Kitamichi,
Electronics and Communications in Japan (Part III: Fundamental Electronic Science),
pp 13-22, vol 84, no 5, 2001
An Efficient List-Based Scheduling Algorithm for High-Level-Synthesis,
Sllame Azeddien M., Drábek Vladimír,
EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools,
Dortmund, Germany, 2002,
link
Allocation of registers to multiport memories based on
register-interconnect optimization,
Modelling and Simulation, pp. 57-64, vol. 25, no. 4, 1991;
C. A. Mandal, P. P. Chakrabarti, S. Ghose.
Traffic-Aware Consistent Flow Migration in SDN,
2020 IEEE International Conference on Communications (ICC):
Next-Generation Networking and Internet Symposium,
pp 1–6, 7–11 June, 2020;
Ilora Maity, Sudip Misra, Chittaranjan Mandal
SamaTulyataOne: A Path Based Equivalence Checker
[tool paper],
12th Innovations in Software Engineering Conference,
Pune, India, Feb 14-16, 2019 (ISEC 2019),
Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
An Equivalence Checking Framework for Array-Intensive Programs
[tool paper],
15th International Symposium on Automated Technology for Verification
and Analysis,
Pune, India, Oct 3-6, 2017 (ATVA 2017), LNCS vol 10482, pp 84-90,
Kunal Banerjee, Chittaranjan Mandal, Dipankar Sarkar
SamaTulyata: An Efficient Path Based Equivalence Checking Tool
[tool paper],
15th International Symposium on Automated Technology for Verification
and Analysis,
Pune, India, Oct 3-6, 2017 (ATVA 2017), LNCS vol 10482, pp 109-116,
Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar,
Chittaranjan Mandal
Verification of KPN level transformation,
Proceedings of 26th IEEE International Conference on VLSI Design,
Hyatt Regency, Pune, India, pp 338-343, January 5-10, 2013,
Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
Workload Driven Power Domain Partitioning,
Proceedings of the 16th International Symposium on
VLSI Design and Test
Bengal Engineering and Science University, Shibpur, India;
July 1-4, 2012,
Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta and
Chittaranjan Mandal
Verification of Register Transfer Level Low Power Transformations,
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
2011,
Chennai, India, pp 313-314, July 4-6, 2011,
Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
(Abstract/PDF paper)
A. Vinay, K. G. Abhijit, M. Saifulla, D. Jayashree, and T. N. Anitha.
2011. A comparative analysis of centralized and distributed dynamic
load balancing algorithms for cluster based video-on-demand systems. In
Proceedings of the International Conference & Workshop on Emerging
Trends in Technology (ICWET '11). ACM, New York, NY, USA, 351-356.
link
Optimal specification of a receiver blocks from global specifications:
Example of IEEE 802.15. 4Optimal specification of a receiver blocks
from global specifications: Example of IEEE 802.15. 4Optimal
specification of a receiver blocks from global specifications: Example
of IEEE 802.15. 4,
Ndungidi, P. and Dongmo, U. and Dualibe, F. and Valderrama, C.
link
Automatic Detection of Human Fall in Video,
Proceedings of Second International Conference on Pattern
Recognition and Machine Intelligence (PReMI'07),
Calcutta, India, pp 616--623, December 18-22, 2007,
Vinay Vishwakarma, Chittaranjan Mandal, Shamik Sural
(Abstract)
Fall detection and activity recognition with machine learning
Luštrek, B Kaluža - Informatica, 2009
link
How to detect human fall in video? An overview,
J Willems, et. al.
link
Hand-in-hand verification of high-level synthesis,
Proceedings of IEEE 17th great lakes symposium on Great lakes symposium on VLSI
(GLSVLSI'07)
Stresa-Lago Maggiore, Italy, pp 429--434, March 11-13, 2007,
Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Chris Reade
(Abstract / PDF paper)
Youngsik Kim , Nazanin Mansouri,
Automated formal verification of scheduling with speculative code motions,
Proceedings of the 18th ACM Great Lakes symposium on VLSI,
May 04-06, 2008, Orlando, Florida, USA,
link
A Scheme for Recipient Specific Yet Anonymous and Transferable
Electronic Cash
Proc. of WEBIST 2007
Barcelona, Spain, Setúbal, pp 204-209, March 3-6, 2007,
Chittaranjan Mandal, Chris Reade,
(Abstract / PDF paper)
High Performance Sleep-Wake Sensor Systems Based on Cyclic Cellular Automata,
Y. M. Baryshnikov, E. G. Coffman, K. J. Kwak,
Proceedings of the 7th international conference on Information processing in sensor networks,
pp 517-526, 2008
link
An Energy-Driven Adaptive Cluster Head Rotation Algorithm for Wireless Sensor
Networks;
Huang He-qing; Shen Jie; Yao Dao-yuan; Ma Kui; Liu Hai-tao;
Journal of Electronics & Information Technology, 2009, vol 31(5), pp 1040-1044,
ISSN: 1009-5896, CN: 11-4494/TN
A Formal Approach for High Level Synthesis of Linear Analog Systems,
Proceedings of ACM/IEEE GLSVLSI 2006,
Philadelphia, USA, pp 345-348, April 30 -- May 2, 2006,
Soumya Pandit, Chittaranjan Mandal, Amit Patra
(Abstract / PDF paper)
Thanyapat Sakunkonchak, Takeshi Matsumoto, Hiroshi Saito, Satoshi Komatsu,
Masahiro Fujita, Equivalence checking in C-based system-level design by
sequentializing concurrent behaviors, Proceedings of the third conference on IASTED
International Conference: Advances in Computer Science and Technology, pp 36-42, April
02-04, 2007, Phuket, Thailand,
link
Shunsuke Sasaki, Tasuku Nishihara, Daisuke Ando, Masahiro Fujita,
Hardware/Software Co-design and Verification
Methodology from System Level Based on System
Dependence Graph,
Journal of Universal Computer Science, vol. 13, no. 13, pp 1972-2001, 2007,
link
Bijan Alizadeh and Masahiro Fujita,
Sequential Equivalence Checking Using a Hybrid
Boolean-Word Level Decision Diagram,
CSICC 2008, CCIS 6, pp. 697704, 2008,
link
Bijan Alizadeh and Masahiro Fujita,
A Hybrid Approach for Equivalence Checking Between
System Level and RTL Descriptions,
IWLS07, USA, pp. 298-304, 2007,
link
B. Alizadeh, M. Fujita,
Automatic Merge-point Detection for Sequential Equivalence Checking of
System-level and RTL Descriptions, ATVA07, Japan, pp. 129-144, 2007,
link
Sudipta Kundu, Sorin Lerner, and Rajesh Gupta,
Validating High-Level Synthesis,
Proceedings of the 2008 International Conference on Computer-Aided Verification (CAV),
pp 459-472, 2008,
link
Sudipta Kundu, Sorin Lerner and Rajesh Gupta,
High-Level Verification,
IPSJ Transactions on Systems LSI Design Methodology,
vol 2, pp 131-144, August, 2009
Lars Gesellensetter, Sabine Glesner, and Elke Salecker,
Formal Verification with Isabelle/HOL in
Practice: Finding a Bug in the GCC Scheduler,
FMICS 2007, pp 85-100,
link
Tsung-Hsi Chiang and Lan-Rong Dung,
Verification of Dataflow Scheduling,
International Journal of Software Engineering
and Knowledge Engineering and Knowledge Engineering
Vol. 18, no. 6, pp 737-758, 2008,
link
Tsung-Hsi Chiang, Lan-Rong Dung, Verification method of dataflow algorithms in
high-level synthesis, Journal of Systems and Software, v.80 n.8, p.1256-1270, August,
2007, link
Data aggregation in wireless sensor networks using ant colony algorithm,
Wen-Hwa Liao, Yucheng Kao, Chien-Ming Fan,
Journal of Network and Computer Applications,
pp 387-401, vol 31, no 4, Nov 2008, link
Introducing an ACO Based Paradigm for Detecting Wildfires using Wireless Sensor Networks,
R Chandrasekar, Sudip Misra,
International Symposium on Ad Hoc and Ubiquitous Computing, 2006. (ISAUHC '06),
pp 112-117, 20-23 Dec 2006,
link
Probabilistic Ant based Clustering for Distributed Databases,
Chandrasekar, R.; Vijaykumar, V.; Srinivasan, T.,
3rd International IEEE Conference on Intelligent Systems, Sept. 2006, pp 538-545
link
An Ant Odor Analysis Approach to the Ant Colony Optimization Algorithm for Data-Aggregation,
Vijaykumar, V.; Chandrasekar, R.; Srinivasan, T.,
International Conference on Wireless Sensor Networks, Wireless
Communications, Networking and Mobile Computing (WiCOM 2006),
pp.1-4, 22-24 Sept. 2006,
link
A probabilistic zonal approach for swarm-inspired wildfire detection using sensor networks,
Chandrasekar Ramachandran, Sudip Misra, Mohammad S. Obaidat,
International Journal of Communication Systems,
vol 21, no 10, 2006, pp 1047-1073,
link
Animating Algorithms over the Web
Proc. of WEBIST 2006,
Setúbal, Portugal, pp 403-407, Apr 11-13, 2006,
Chittaranjan Mandal, Chris Reade,
ISBN 978-9728865-47-4.
(Abstract / PDF paper)
A System for Automatic Evaluation of Programs for Correctness and Performance
Proc. of WEBIST 2006,
Setúbal, Portugal, pp 196-203, Apr 11-13, 2006,
Amit Kumar Mandal, Chittaranjan Mandal, Chris Reade,
ISBN 978-9728865-47-4.
(Abstract / PDF paper)
Verification of Scheduling in High-level Synthesis,
Proceedings of IEEE Computer Society Annual Symposium on VLSI,
Karlsruhe, Germany, pp 141-146, Mar 2-3, 2006,
Chandan Karfa, S R Pentakota, Chittaranjan Mandal, Dipankar Sarkar,
Chris Reade.
(Abstract / PDF paper)
A Technique for Algorithm Animation Over the Web,
Proc. of International Conference on Emerging Applications of IT,
Elsevier,
Science City, Calcutta, pp 163-166, Feb 10-11, 2006,
Chittaranjan Mandal, Chris Reade.
(Abstract / PDF paper)
High-level Synthesis of Linear Analog Systems,
Proc. of International Conference on Emerging Applications of IT,
Elsevier,
Science City, Calcutta, pp 389-392, Feb 10-11, 2006,
Soumya Pandit, Chittaranjan Mandal, Amit Patra.
(Abstract / PDF paper /
slides)
An Efficient Algorithm for scheduling verification,
Proc. of International Conference on Emerging Applications of IT,
Elsevier,
Science City, Calcutta, pp 397-400, Feb 10-11, 2006,
Chandan Karfa, S R Pentakota, Chittaranjan Mandal, Dipankar Sarkar,
Chris Reade.
(Abstract / PDF paper)
Design and Implementation of an Automatic Program Evaluation System,
Proc. of International Conference on Emerging Applications of IT,
Elsevier,
Science City, Calcutta, pp 325-328, Feb 10-11, 2006,
Amit Mandal, Chittaranjan Mandal, Chris Reade.
(Abstract / PDF paper)
Optimal Clustering in Sensor Networks Using Game-theoretic
Particle Swarm Optimization,
Proc. of the 4th Asian International Mobile Computing Conference
(AMOC 2006),
Hyatt Regency, Calcutta, India, pp 114-118, Jan 4-7, 2006,
Rajiv Misra, Chittaranjan Mandal,
ISBN: 0-07-060834-2.
(Abstract / PDF paper)
An Improved Energy Efficient Distributed Clustering
Algorithm for Large Wireless Sensor Networks,
Proc. of the 4th Asian International Mobile Computing Conference
(AMOC 2006),
Hyatt Regency, Calcutta, India, pp 95-104, Jan 4-7, 2006,
Rajiv Misra, Chittaranjan Mandal,
ISBN: 0-07-060834-2.
(Abstract / PDF paper)
Self-Healing for Self-Organizing Cluster Sensor Networks,
Proc. of IEEE 2006 Annual India Conference (INDICON 2006),
India Habitat Centre, New Delhi, India, Sept 15-17, 2006,
Rajiv Misra, Chittaranjan Mandal
Network Reconfiguration for Energy Efficient Clustering of Wireless Sensor Networks,
Dujdow Buranapanichkit, Ekavic Chanpen, Proceedings of the 23rd International Technical
Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), 2008, link
SAST: An Interconnection Aware High-Level Synthesis Tool,
Proc. of the 9th VLSI Design & Test Symposium (VDAT),
Bangalore, India, pp 285-293, August 11-13, 2005,
C R Mandal, D Sarkar, C Karfa, J S Reddy, S Biswas.
(Abstract / PDF paper / Slides)
Jaime Lloret, Miguel Garcia and Jesus Tomas,
Improving Mobile and Ad-hoc Networks performance using Group-Based
Topologies, Wireless Sensor and Actor Networks II,
pp 209-220, 2008, ISBN: 978-0-387-09440-3
link
Muhmmad Ijaz, TCP performance evaluation in MANET, MSc in Electrical
Engineering, Blekinge Instute of Technology, March 2009
link
A Web-based Automatic Evaluation System,
Proc. of the 3rd European Conference on eLearning,
Paris, France, pp 189-196, 25-26 November 2004,
C Mandal, V L Sinha, C M P Reade.
(Abstract / Extended abstract / PDF paper / presentation slides)
A New Approach to Timing Analysis using Event Propagation and
Temporal Logic,
Proceedings of DATE '04,
Paris, France, pp 1198 - 1203, 2004,
Arijit Mondal, Partha P Chakrabarti, C Mandal.
(Abstract / PDF paper)
A Web-Based Course Management Tool,
Proc. of the 2nd European Conference on e-Learning,
Nov 6-7, Glasgow, UK, pp 293-302, 2003,
C. Mandal, V. L. Sinha, C. M. P. Reade.
(Abstract / PDF paper)
Timing Analysis of Tree-like RLC Circuits,
Proceedings of IEEE International Symposium on Circuits and Systems,
Scottsdale, Arizona, USA, pp. 838-841, 2002,
Rajendran, B., Kheterpal, V., Das, A., Majumder, J.,
Mandal, C., Chakrabarti, P.P.
(Abstract / PDF paper)
Nikolaos G. Bourbakis , M. Mortazavi, A VLSI DESIGN DESIGN-SYNTHESIS
METHODOLOGY AT THE TRANSISTOR LAYOUT LEVEL, Journal of Integrated Design
& Process Science, v.9 n.3, p.63-85, July 2005,
link
Nikolaos G. Bourbakis, A generic, formal language-based methodology for
hierarchical floorplanning-placement, Computer Languages, Systems and
Structures, v.34 n.1, p.25-42, April, 2008,
link
Integrated Scheduling and Allocation for Synthesis of Structured
Data Paths,
Proceedings of IEEE VLSI Design & Test Workshops, August 6-7, 1998,
The Habitat World, Lodi Road, New Delhi, India,
on-line proceedings;
C. Mandal, R. Zimmer.
(Abstract)
Efficient Scheduling for Design Exploration with Imprecise
Latency and Register Constraints,
Chantrapornchai Chantana, Surakumpolthorn Wanlop, SHA Edwin
pp 259-270, Embedded and ubiquitous computing, 2004,
link
An Indexed Bibliography of Genetic Algorithms in Electronics and VLSI Design and
Testing, A. Jarmo, 1994,
link
Port Assignment for Dual and Triple Port Memories Using a Genetic
Approach,
Proceedings of IFIP Asia/Pacific Conference on Hardware Description
Languages,
Bangalore, INDIA, pp. 60-64, 1996;
C. A. Mandal, P. P. Chakrabarti, S. Ghose.
(Abstract / postscript paper)
A Framework for High Level Synthesis, International Workshop on
Artificial Intelligence, I.I.M., Calcutta, March, 1994;
C. A. Mandal, P. P. Chakrabarti, S. Ghose.
Complexity of Scheduling 2-Operation Chains and Some Other
Related Scheduling Problems,
Proceedings of the Fourth National Seminar on Theoretical
Computer Science,
IIT Kanpur, INDIA, pp. 171-180, 1994;
C. A. Mandal, P. P. Chakrabarti, S. Ghose.
Workshop on Railway Signalling Automation using
(SigDATE),
conducted through CEP (IIT/CEP/WOR/WOR/2023-2024/CS/178) at IIT Kharagpur, Apr 22-23, Apr 25-26, Apr 29-30, May 2-3, May 6-7, 2024;
Chittaranjan Mandal
Workshop on Railway Signalling Automation
for Indian Railway Signalling Engineers towards adoption of
developed
signal Interlocking tool for SIP capture and RCC generation
(SigDATE),
conducted through CEP (IIT/CEP/WOR/WOR/2022-2023/CS/61
) at IIT Kharagpur, Aug 4-5, Aug 22-23, Aug 25-26, 2022;
Chittaranjan Mandal
J P Mohanty, Chittaranjan Mandal,
Connected Dominating Set in Wireless Sensor Network,
in
Handbook of Research on Advanced Wireless Sensor Network Applications,
Protocols, and Architectures,
IGI Global, Aug 2016 (ISBN: 1522504869)
Ariyam Das, Chittaranjan Mandal and Chris Reade,
A Survey of CDS Construction Techniques for Ad hoc Sensor Networks,
in Wireless Sensor Networks From Theory to Applications, pp 247-264,
Ibrahiem M M El Emary and S Ramakrishnan (Eds.),
CRC Press, Aug 2013 (ISBN: 978-1-4665-1810-0)
Vinay Viswakarma, Shamik Sural and Chittaranjan Mandal,
Fall
Detection from a Video in the Presence of Multiple Persons,
in
Machine Interpretation of Patterns: Image Analysis and Data Mining,
R. K. De, D. P. Mandal and A. Ghosh (Eds.), Chapter 9, pp 167-193,
World Scientific Press, Jan 2010, (ISBN: 978-981-4299-18-3).
Mandal, A., Mandal, C., Reade, C. (2009),
Interface and Features for an Automatic 'C' Program Evaluation System,
in
Solutions and Innovations in Web-Based Technologies for Augmented Learning:
Improved Platforms, Tools and Applications
by Nikos Karacapilidis (Ed.),
Chapter X,
pp. 168-185,
IGI Global, Feb 2009 (ISBN: 978-1-60566-238-1).
Mandal, A, Mandal, C, Reade, C,
A System for Automatic Evaluation of Programs for
Correctness and Performance,
in J. Filipe, J. Cordeiro, and V. Pedrosa (Eds.),
Web Information Systems and Technologies I, pp. 367-380,
Lecture Notes in Business Information Processing (LNBIP),
Springer-Verlag, Berlin-Heidelberg, Mar 2007
(ISBN: 978-3-540-74062-9)
Patents
System for Design of Route Control Chart and Application Logic for
Interlocked Signalling,
Shankhadip Mallick, Manoja Rajalakshmi Aravindakshan, Chittaranjan Mandal,
and Amit Misra,
patent application no. 202431029893, filed on Apr 12, 2024
Computing system for running computationally intensive software application in
computing device having limited computational resource,
Lahoria Rahul and Mandal Chittaranjan,
patent no. IN201400832I2, filed on 2014-08-07, published on 2016-08-26
Chittaranjan Mandal,
Advanced System Architecture CAD [Part II]: System on Chip,
prepared as learning material for
the Special Manpower Development Program for
Ministry of Information Technology, India, September 2004.