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Aritra Hazra

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Dr. Aritra Hazra is currently an Assistant Professor in the Department of Computer Science and Engineering (CSE) at Indian Institute of Technology (IIT) Kharagpur. Prior to joining IIT Kharagpur, he also served as an Assistant Professor in the Department of CSE at IIT Madras from August 2015 to July 2017. Earlier, he did his Bachelor of Engineering (B.E.) from the Department of CSE at Jadavpur University (Kolkata) in 2006. He received his Master of Science (M.S.) degree in 2010 and earned his Doctor of Philosophy (Ph.D.) degree in 2015, both from the Department of CSE at IIT Kharagpur.

Dr. Hazra's research interest lies broadly on the areas of Formal Methods, Design Verification, VLSI CAD, Artificial Intelligence and Machine Learning. He has published many research articles in several leading journals and well-known conferences, including two best student paper awards in VLSI Design Conferences (in 2010 and 2017). He also received several accolades for his PhD work, including ACM (India) Best PhD Dissertation Award 2015 and IESA Technovation – TechnoInventor (Ph.D.) Award 2015.

Besides, Dr. Hazra was a recipient of INAE (Indian National Academy of Engineering) Young Engineer Award in 2017 and is an Young Associate of INAE since then. He was also awarded the Associateship of IASc. (Indian Academy of Science) in 2018, IEI (The Institute of Engineers India) Young Engineer Award in 2019 and Institute Faculty Excellence Award (Assistant Professor) in 2021. He is a member of IEEE (Institute of Electrical and Electronics Engineers) and a professional member of ACM (Association for Computing Machinery).

and ... an illeist is a person who refers to himself in the third person.

Be yourself; everyone else is already taken. (Oscar Wilde)

2015:   Doctor of Philosophy (Ph.D.)

2010:   Master of Science (M.S.)

2006:   Bachelor of Engineering (B.E.)

2002:   Higher-Secondary (Class XII Board Exam)

2000:   Secondary (Class X Board Exam)

Education is the manifestation of the perfection already in man. (Swami Vivekananda)

Assistant Professor   (August 2017 – Present)

Assistant Professor   (August 2015 – July 2017)


Research Associate (September 2014 – July 2015)

Research Scholar (January 2007 – July 2014)

Research Consultant (August 2006 – August 2014)

The only source of knowledge is experience. (Albert Einstein)

Current Semester     [ 2025 – Spring ]


Previous Semester     [ 2024 – Autumn ]

It is the supreme art of the teacher to awaken joy in creative expression and knowledge. (Albert Einstein)

Theory:


Laboratory:

Those who know, do. Those that understand, teach. (Aristotle)

Theory:
    Course Number Subject Name Session (WebLink)
    CS2700 Programming and Data Structures 2016 Odd
    CS6760 Digital Design Verification 2017 Even
    2016 Even
    ID 6021 Introduction to Research 2015 Odd


Laboratory:
    Course Number Subject Name Session (WebLink)
    CS2710 Programming and Data Structures 2016 Odd

In learning you will teach, and in teaching you will learn. (Phil Collins)

    Year Session/Semester Course/Subject Instructor
    2015 Spring Database Management Systems Prof. Pallab Dasgupta
    2013 Spring CAD for VLSI Prof. Indranil Sengupta
    Autumn Programming and Data Structure (Theory) Prof. Partha Pratim Chakrabarti
    2012 Spring CAD for VLSI Prof. Dipanwita Roy Chowdhury
    Autumn Embedded Software Design and Validation (Theory + Lab) Prof. P. Dasgupta, Prof. P. P. Chakrabarti and Prof. R. Mall
    2011 Spring CAD for VLSI Prof. Chittaranjan Mandal
    Autumn Embedded Software Design and Validation (Theory + Lab) Prof. P. Dasgupta, Prof. P. P. Chakrabarti and Prof. R. Mall
    2010 Spring Distributed Systems Prof. Pallab Dasgupta
    Autumn Foundations of Computing Science Prof. Pallab Dasgupta
    2009 Spring CAD for VLSI Prof. Partha Pratim Chakrabarti
    Autumn Graph Theory Prof. Pallab Dasgupta
    2008 Spring Distributed Systems Prof. Pallab Dasgupta
    Autumn Programming and Data Structure (Theory) Prof. Sudeshna Sarkar
    2007 Autumn Graph Theory Prof. Pallab Dasgupta
    2006 Autumn Graph Theory Prof. Pallab Dasgupta

Tell me and I forget. Teach me and I remember. Involve me and I learn. (Benjamin Franklin)

    Year Month Course/Program Session Title
    2024 July AICTE QIP PG Certificate Programme in AI and ML AI and ML in Games (Lecture)
    Reinforcement Learning (Lecture)
    2022 December Bangladesh-Bharat Digital Service and Employment Training (BDSET) Logic and Deduction in AI (Lecture)
    Constraint Satisfaction Problems in AI (Lecture)
    Reinforcement Learning: An Overview (Lecture)
    2019 November Synopsys Employee Training Program Design Verification (Lecture+Lab: one-week course)
    2014 June International Summer and Winter Term (ISWT) Advanced Formal Techniques in Design, Verification and Testing of Digital Integrated Circuits (Lab)
    2012 May Advanced VLSI Summer Course Assertions in Design Verification (Lecture + Lab)
    September Interra Systems Employee Training Program Design Verification (Lab)
    2011 March Interra Systems Employee Training Program Simulation and Assertion-based Verification (Lecture + Lab)
    Formal Verification Tools and Applications (Lecture + Lab)
    May Advanced VLSI Summer Course Assertions in Design Verification (Lecture + Lab)
    August Interra Systems Employee Training Program Formal Specification and Design Verification (Lecture + Lab)
    December Formal Verification Tools - NuSMV and Magellan (Lab)
    2010 May Advanced VLSI Summer Course Assertions as Applied to Design Verification (Lecture + Lab)
    December Interra Systems Employee Training Program Formal Verification Tools and Applications (Lecture + Lab)
    2009 May Advanced VLSI Summer Course Simulation and Assertion-based Verification (Lecture + Lab)
    2008 May Advanced VLSI Summer Course Assertion-based Verification (Lecture + Lab)
    Testing and Design for Testability (DFT) (Lecture)
    2006 December Interra Systems Employee Training Program NuSMV - A New Symbolic Model Verifier Tool (Lab)

When one teaches, two learn. (Robert Heinlein)

Formal Methods for Safety-Critical System Design and Validation:
    Formal methods specify rigorous theoretical and mathematical models to design software and hardware systems and use formal techniques to validate and certify the design behaviors, ensuring its correctness, power management, reliability, security, quality and robustness attributes. We primarily aim to design automated frameworks for the following aspects:
    • Functional correctness of integrated circuit designs during various phases (both in pre-silicon as well as post-silicon) leveraging simulation, formal as well as semi-formal techniques
    • Comprehensive verification of the power management strategy for integrated circuits involving the digital power manager orchestrating the analog power control circuitry
    • Reliability and robustness analysis of safety-critical systems from formal specifications of spatial and temporal redundancy artefacts, properties of the error-free system, error probabilities of the control components, and reliability targets

Computer-Aided Design (CAD) for Security:
    VLSI designs and integrated circuits are manufactured using several CAD frameworks where many challenging algorithmic problems need to be solved, including design synthesis, floor-planning, placement and routing, to deliver a final chip. We primarily focus on the following aspects:
    • Vulnerability assessment of cryptographic primitives in secure cipher designs with respect to fault attacks and synthesis of automatic countermeasures to mitigate security flaws in cipher algorithms as well as their hardware or software implementations
    • Developing strong physically unclonable function (PUF) designs and its compositions which are resilient to machine learning attacks, leveraging CAD based testability and formal learnability analysis frameworks, justifying the responsiveness, unclonability, reliability, correlation and learnability factors of PUFs

Robust Explainability of Machine Learning Models:
    Explainability is becoming one of the key needs for widespread adoption of ML approaches in safety-critical applications. We primarily target to explore and devise approaches for comprehensive interpretability as well as ensure robustness of trained ML models so that it cannot be fooled or manipulated by adversarial/malicious perturbations.

[ Please Visit Formal Methods Research Group Page for More Details ]

Imagination is more important than knowledge. For knowledge is limited to all we know and understand, while imagination embraces the entire world, and all there ever will be to know and understand. (Albert Einstein)


                                       





If you have done something good, try to write. If you have written something proper, try to publish. If you have published well, try to write a thesis. (Anonymous)

United States Patent No. US2024/0193337A1
  • Title:   Tracking Coverage Artifacts for Periodic Signals using Sequence-based Abstractions
  • Inventors:   Ayan Chakraborty, Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian and Mohammad Moshiur Rahman
  • Status:   Granted
  • Application No.:   US18/076,547
  • Filing Date:   07-December-2022
  • Issuing Date:   13-June-2024

United States Patent No. US2023/0176100A1
  • Title:   Identifying Glitches and Levels in Mixed-Signal Waveforms
  • Inventors:   Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar Surendran and Lakshmanan Balasubramanian
  • Status:   Granted
  • Application No.:   US18/071,917
  • Filing Date:   30-November-2022
  • Issuing Date:   08-June-2023

Patents are like fertilizer. Applied wisely and sparingly, they can increase growth. (Alex Tabarrok)

2024 July:    AI in Strategic Game Playing

2024 March:    Learning to Become Experts in Playing Games: A Time-Traversal through AI Eras

2023 July:    Policy Optimization in Reinforcement Learning

2023 June:    Tryst with Infinity: A Mathematical Poetry

2019 December:    Formal Verification for CPS Security Assurance

2018 July:    PAC Learnability of PUFs

2018 July:    Formal Methods for Fault Attack Vulnerability Analysis in Block Ciphers

2017 March:    Formal Methods for Security Analysis

2016 June:    Formal Methods for Power Intent Verification

2016 January:    Formal Methods for Power Intent Validation in Integrated Circuits

2014 July:    Formal Methods for Architectural Power Intent Verification

2014 July:    Embedded Control Scheduling: Automata and Language Theoretic Perspective

2014 March:    Design of Reliable Embedded Control Systems

If you can't explain it simply, you don't understand it well enough. (Albert Einstein)

As Principal Investigator (PI):



As Joint Principal Investigator (Joint-PI):



As Co-Principal Investigator (Co-PI):


If you keep proving stuff that others have done, getting confidence, increasing the complexities of your solutions - for the fun of it - then one day you'll turn around and discover that nobody actually did that one! And that's the way to become a computer scientist. (Richard Feynman)

As Principal Investigator (PI):



As Joint Principal Investigator (Joint-PI):



As Co-Principal Investigator (Co-PI):


Practice makes perfect. After a long time of practicing, our work will become natural, skillfull, swift, and steady. (Bruce Lee)

As Research Consultant @ IITKGP:



Collaborative Student Projects @ JU and @ IITKGP:

  • Android App Development
    • Exploratory Projects:
      • TiltU: A novel technique for unlocking android-enabled device by detecting pre-defined tilt patterns
      • BlueMouse: Using an android-enabled device as a wireless physical mouse (via Bluetooth)
    • Duration:   February 2013 – March 2013
    • Contributors: Aritra Hazra and Tamal Sen

  • Modification of Gunfinder-Studio Software

You can't plant a seed without getting your hands dirty. (Mariah Dillard)

PARLE-G : A CAD Tool for Automated Assessment of Provable Learnability from PUF Representations
  • Summary:   This tool analyzes the PAC-learnability of PUF designs from an architectural level. To enable this, we propose a formal PUF representation language (PUF-G) by which any architectural PUF design and its compositions can be specified upfront. This PUF specification can be automatically analyzed through this tool by translating the same to an interim model and finally deriving the PAC-learnability bounds from the model. Such a tool will help the designer to explore various compositional architectures of PUFs and its resilience to ML attacks automatically before converging on a strong PUF design for implementation.
  • Status:   Completed – Developed as a part of a DRDO Project

CoveRT : A Coverage Reporting Tool for Analog Mixed-Signal Designs
  • Summary:   This tool is built around a library of standard AMS coverage primitives and a language for defining coverage bins around these primitives. It collects the coverage information by interfacing with standard commercial simulators and save these across simulation runs. The tool can work online with commercial simulators while the simulation executes, or offline by replaying the waveforms collected during simulation.
  • Status:   Completed – Delivered to TI (USA) as part of SRC project for Testing & Development

Fault-Droid : A Tool for Analyzing Information Leakage of Block Ciphers through Fault Attacks
  • Summary:   This tool automatically analyze the vulnerability with respect to fault attacks. It explores the entire fault attack space; identifies the single/multiple fault scenarios that can be exploited by a differential fault attack (DFA); rank-orders them with respect to criticality; and provides design guidance to mitigate the vulnerabilities at low cost. Fault-Droid uses a formal model of fault attacks on a high-level specification of a block cipher and hence is equally applicable to both software and hardware implementation of the cipher.
  • Status:   Completed – Developed as part of a CISCO University Research Grant Project

Power-Trams : A Tool for Formal Verification and Coverage Analysis of Mixed-Signal Power Management
  • Summary:   This tool extracts analog features with latencies and leverage annotated UPF specifications to generate formal properties in order to validate the mixed-signal power management logic. The properties are generated considering the power management for both the analog as well as digital power domains. It also provides a formal analog assertion template where analog domain experts can fill in analog behaviors with their built-in domain knowledge, so that formal properties are gleaned out and used in verification. Further, it supports a framework for formal coverage analysis of PML leveraging auxiliary power machine, thereby providing a comprehensive verification as well as coverage analysis flow.
  • Status:   Completed – Delivered to Intel Inc. (USA) for Testing

Power-Tructor : A Tool for Formal Verification and Coverage of Architectural Power Intent
  • Summary:   This tool extracts per-domain assertions (in SVA) from UPF-specifications and leverage these synthesized assertions to formulate the architectural power intent properties. Finally, this tool invokes Magellan tool (of Synopsys) to formally verify those generated assertions over the power control logic of a design. Moreover, this tool is also capable of analyzing the global power state coverage of the power management logic. Interestingly, the tool can handle the power management strategy implemented partially in hardware and partially in software/firmware.
  • Status:   Completed – Delivered to Synopsys Inc. (USA) for Productization

SoC-Residency-Simulator : A Power-Performance Evaluator for Given Workloads
  • Summary:   This tool is built on top of some existing SystemVerilog simulator. The tool takes as input a given partition of the SoC components into power domains and a software strategy for deciding the residencies. It runs on various workloads to analyze the performance of the integrated power management and produce a report on the power consumption/wastage of each components of the design. This solution will also help to re-organize the components and power domains of a design to get better power utilization profile.
  • Status:   Completed – Delivered to Intel Corp. (India) for In-house Experiments

CovAnalyzer : A Completeness Checker for Design Specifications
  • Summary:   This tool analyzes the completeness of a formal specification against a given fault model. Current tool considers single stuck-at-fault on the interface signals as the fault model and supports specifications written in various temporal languages like LTL, ForSpec (of Intel Corp.) or SVA.
  • Status:   Completed – Delivered to Intel Corp. (USA) for Productization

For a successful technology, reality must take precedence over public relations, for nature cannot be fooled. (Richard Feynman)


Ask nothing; want nothing in return. Give what you have to give; it will come back to you, but do not think of that now. (Swami Vivekananda)


    Ongoing:
      Mithun Kumar Mahto (July 2024 – Present)
      • Thesis Topic:   Formal Methods for Verification of Machine Learning Models

      Madhumanti Bhattacharyya (July 2023 – Present):   Co-supervised with Dr. Rajlakshmi Guha (Assistant Professor, RCESH, IIT-KGP)
      • Thesis Topic:   Artificial Intelligence and Cognitive Neuropsychology

      Debjyoti Das Adhikary (September 2020 – Present):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Topic:   Frameworks for Explainable and Interpretable Artificial Intelligence

      Soumi Chatterjee (January 2020 – Present):   Co-supervised with Dr. Debdeep Mukhopadhyay (Professor, CSE, IIT-KGP)
      • Thesis Topic:   CAD for PUF and Hardware Security

      Sourav Das (January 2019 – Present):   Co-supervised with Dr. Pallab Dasgupta (Professor, CSE, IIT-KGP)
      • Thesis Topic:   A Comprehensive Verification Planning and Coverage Management Framework



    Completed:

      Durba Chatterjee (July 2018 – February 2024):   Co-supervised with Dr. Debdeep Mukhopadhyay (Professor, CSE, IIT-KGP)
      • Thesis Title:   Formal Methods for Design and Analysis of Physically Unclonable Functions
      • Recognitions:   Intel PhD Fellowship 2021, Best PhD-Forum Poster Award at AsianHost 2021
      • Next Position:   Postdoctoral Researcher at Radboud University (Nijmegen, Netherlands)

      Sudipa Mandal (July 2015 – March 2022):   Co-supervised with Dr. Pallab Dasgupta (Professor, CSE, IIT-KGP)
      • Thesis Title:   Management and Verification of Power and Thermal Contracts in Integrated Circuits
      • Recognition:   Best Student Paper Award in VLSID 2017
      • Next Position:   Intel Inc. (Bangalore, India)


    Ongoing:
      Coming Soon ...


    Completed:
      Sunandan Adhikary (July 2018 – July 2021):   Co-supervised with Dr. Soumyajit Dey (Assistant Professor, CSE, IIT-KGP)
      • Thesis Title:   Exploring Platform-aware Formal Methods for Safe and Secure Cyber-Physical Systems
      • Next Position:   Pursuing Ph.D. from CSE at IIT Kharagpur (India)

      Indrani Roy (July 2016 – May 2019):   Co-supervised with Dr. Chester Rebeiro (Assistant Professor, CSE, IIT-M)
      • Thesis Title:   Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations
      • Recognition:   Biswajit Sain Endowment Prize for Best MS Thesis
      • Next Position:   Apple Inc. (Bangalore, India)


    Ongoing:
      Lalita Purohit (January 2024 – Present)
      • Thesis Topic:   Adversarial Robustness via Comprehensive Image Explanation

      Swathi Janapala (January 2024 – Present)
      • Thesis Topic:   Human versus Machine Cognitive Approaches in Visuo-Spatial Problem Solving


    Completed:
      Akash Kundu (January 2023 – May 2024)
      • Thesis Title:   A Layered Approach to Comprehensive Image Explanation
      • Next Position:   CNH Industrial Pvt. Ltd. (Gurugram, India)

      Anchal Singh (July 2022 – May 2023)
      • Thesis Title:   Educational Tool Creation for Visualization of Graph Algorithms
      • Next Position:   Unknown

      Nabajyoti Das (January 2021 – May 2022):   Co-supervised with Dr. Pallab Dasgupta (Professor, CSE, IIT-KGP)
      • Thesis Title:   Automatic Test Generations from SystemVerilog Assertions
      • Next Position:   Samsung Inc. (Delhi, India)

      Sandeep Kumar Shahu (January 2021 – May 2022):   Co-supervised with Dr. Pallab Dasgupta (Professor, CSE, IIT-KGP)
      • Thesis Title:   Dummy Load Redistribution Attack on Power System
      • Next Position:   Intel Inc. (Bangalore, India)

      Sudipta Paria (January 2019 – May 2020)

      Subham Saha (January 2019 – May 2020):   Co-supervised with Dr. Pabitra Mitra (Professor, CSE, IIT-KGP)
      • Thesis Title:   Developing Attack Graph based Security Measures for Networks with Intrusion Detection Systems
      • Next Position:   Microsoft Research (Bangalore, India)

      Gangwal Shubham Santosh (January 2018 – May 2019)
      • Thesis Title:   Understanding Power Management Policies leveraging Task Scheduling of Workload Patterns
      • Next Position:   AppDynamics (Bangalore, India)

      Ginju V. George (June 2016 – May 2017)
      • Thesis Title:   Resource Estimation from Reliability Specifications in Embedded Cyber-Physical Systems
      • Recognition:   Nominated for Departmental Best M.Tech. Thesis
      • Next Position:   VSCC-ISRO (Trivandrum, India)


    Ongoing:
      Choda Y B V Anjaneya (July 2024 – Present)
      • Thesis Topic:   Avoidance of Adversarial Inference through Comprehensive Explainability of Images

      Meduri Harshith Chowdary (July 2024 – Present)
      • Thesis Topic:   Safe-RL Policy Synthesis and Optimization

      Roddur Majumdar (July 2024 – Present)
      • Thesis Topic:   Formal Methods for Consistent and Complete Explainability for Videos

      Yash Sirvi (July 2024 – Present)
      • Thesis Topic:   Safe-RL Policy Synthesis and Optimization

      Adyan Rizvi (June 2024 – Present)
      • Thesis Topic:   Explainability in RL

      Soumojit Bhattacharya (June 2024 – Present)
      • Thesis Topic:   Multi-Agent RL

      Sreyas Venkatraman (June 2024 – Present)
      • Thesis Topic:   Meta and Multi-Task RL


    Completed:
      Satwik Chappidi (January 2022 – May 2024):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Collision-free Collaborative Multi-Agent RL
      • Next Position:  

      Parth Jindal (January 2022 – May 2024):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Explainable Adversarial Deep Learning
      • Next Position:  

      Aayush Prasad (January 2021 – May 2023):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Explainable Diagnosis of Cognitive Impairments using Artificial Intelligence
      • Next Position:   Squarepoint Capital (Bangalore, India)

      Cheepurupalli Udaya Bhaskar (January 2021 – May 2023)
      • Thesis Title:   The Illusion of Stability: A Sentiment Analysis on Algorithmic Stablecoin Failures
      • Next Position:   Microsoft Inc. (Hyderabad, India)

      Sriyash Poddar (January 2021 – May 2023):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)

      Parth Saraf (January 2022 – December 2022)
      • Thesis Title:   ML-based Theorem Selection for Automated Geometry Problem Solving (BTP-I)
      • Next Position:   BTP-II Replaced with Equivalent Subjects

      Harsh Singh (January 2022 – December 2022)
      • Thesis Title:   Formal Methods for Incremental Verification Closure of Digital ICs (BTP-I)
      • Next Position:   BTP-II Replaced with Equivalent Subjects

      Dvij Kalaria (January 2021 – May 2022):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Explainability of Deep Learning and Adversarial Decisions
      • Recognition:   Nominated for Departmental Best B.Tech. Thesis
      • Next Position:   M.S. position at Robotics in Carnegie Mellon University, USA

      Nandini Jalan (January 2021 – May 2022):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Explainable AI: Clock Detection as a CSP
      • Next Position:   Dual-MTP under Prof. Sandip Chakraborty

      Narayan Gupta (January 2021 – May 2022):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   AI based Mechanisms for Screening and Detection of Cognitive Disorders
      • Next Position:   Dual-MTP under Prof. Sandip Chakraborty

      Debajit Chakraborty (January 2021 – May 2022):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Scalable Multi-Agent Reinforcement Learning
      • Next Position:   McKinsey and Company (Gurugram, India)

      Arnab Kumar Mallick (June 2021 – May 2022):   Co-supervised with Dr. Arijit Mondal (Assistant Professor, CSE, IIT-Patna)
      • Thesis Title:   RL Framework for Multi-Agent Movement Optimization under Robotic Warehouse Setup
      • Next Position:   VMock Inc. (Gurugram, India)

      Prakhar Sharma (June 2020 – May 2021):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)

      Chinmay Singh (June 2020 – May 2021):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Emergent Communication and Language in Multi Agent RL Games
      • Next Position:   McKinsey and Co. (Delhi, India)

      Aditya Rastogi (January 2020 – May 2021):   Co-supervised with Dr. Partha Pratim Chakrabarti (Professor, CSE, IIT-KGP)
      • Thesis Title:   Improvements in Self-Supervised Deep Learning and Visualizations
      • Next Position:   Accenture Inc. (Tokyo, Japan)

      Bhukya Raviteja (January 2019 – May 2020)
      • Thesis Title:   A Framework for Automated Enumeration of Instruction and Storage Details for Elementary C-Programs
      • Next Position:   Barklays (Mumbai, India)

      Punit Khanna (January 2016 – May 2017):   Co-supervised with Dr. Chester Rebeiro (Assistant Professor, CSE, IIT-M)
      • Thesis Title:   XFC – A Framework for eXploitable Fault Characterization in Block Ciphers
      • Recognition:   Nominated for Departmental Best Dual-MTP Thesis
      • Next Position:   Goldman Sachs (Bangalore, India)


Don't give students what they want, give them what they need. (Joss Whedon)

Associate Editor:

Technical Program Committee Member:

Reviewer:

The price of greatness is responsibility. (Winston Churchill)

Memberships:
  • INAE Young Associate (2017 – Present)
  • IASc Associate (2018 – 2021)
  • ACM Professional Member (2015 – Present)
  • IEEE Member (2014 – Present)
  • IEEE Graduate Student Member (2008 – 2013)
  • Member of the Governing Body of IEEE Student Branch at IIT Kharagpur (Area: Professional Development, Year: 2010-2011)
  • Member of the Organizing Committee for IEEE-TechSym 2011 (a Technological Symposium organized by IEEE Student Branch at IIT Kharagpur)


Responsibilities @ IITKGP:

  • Departmental (CSE, IIT-Kharagpur)
    • Faculty Adviser:   B.Tech./Dual-Degree 2018-2022/23 Batch
    • Committee Member:
      • UGPEC Representative (April 2022 – Present)
      • Academic Committee (UG) (June 2019 – Present)
      • Faculty Recruitment Committee (July 2023 – Present, September 2020 – May 2022)
      • Admin Committee (July 2019 – April 2022)
      • Faculty Recruitment Committee (September 2020 – May 2022)
      • CSE Webpage Management (October 2017 – June 2018)
      • CDC Representative (September 2017 – June 2018)
      • Departmental Society (August 2017 – June 2018)

  • Institutional (IIT-Kharagpur)
    • Coordinator:   Laboratory and Research in Centre for Artificial Intelligence (May 2018 – December 2020)
    • Member:   Departmental Faculty Recruitment Committee in Centre for Artificial Intelligence (November 2018 – December 2020)


Responsibilities @ IITM:

  • Departmental (CSE, IIT-Madras)
    • Faculty Adviser:   M.Tech. 2015-2017 (15 Students),   M.Tech. 2016-2018 (13 Students)
    • M.Tech. Examiner:  2016 (6 Students),   2017 (8 Students)
    • B.Tech. Examiner:  2017 (4 Students)
    • MS/PhD Research Committee Member:   2016 (1 PhD + 7 MS),   2015 (3 PhD + 2 MS),   2014 (1 MS),   2012 (1 PhD)
    • Committee Member:
      • MS/PhD Entrance Examination (November 2015, April 2016, November 2016, April 2017)
      • Best Doctoral Dissertation Award (2015-2016)

  • Institutional (IIT-Madras)
    • M.Tech. Examiner:   2016 (9 EE Students),   2017 (8 EE Students)
    • MS/PhD Research Committee Member:   2016 (1 MS in EE)

Dedicated to the Service of the Nation (IIT Kharagpur)

Post-Doctoral Positions:
    The Institute has a regularized procedure to appoint post-doctoral researchers. For details, please visit HERE. The standing advertisements/invitations can be found HERE and HERE. Formal applications can be made through ERP portal of the institute. (Interested candidates may write to me with a copy of their recent resume and one letter of recommendation.)

Ph.D. Positions:
    The Institute has a centralized policy for PhD entrance. For details, please visit HERE. Formal applications can be made through ERP portal of the institute. The (CSE) department's Ph.D. enrolment process and syllabus for the PhD entrance test can be found HERE.

M.S. (by Research) Positions:
    For enrolling into M.S., you (must) have to first get through some project with a faulty working in this (CSE) department. The institute project advertisements appear HERE. Once you are already a project staff, you can apply for M.S. The (CSE) department's M.S. enrolment process and syllabus for the M.S. entrance test can be found HERE.

Internship Positions:
    We only offer summer internships and hence please do not apply for internships in winter/fall. For details, please visit HERE. To apply, please visit HERE. (In general, I am not keen to take interns and hence your internship requests directly to my mail-box may never be acknowledged!)

Study hard what interests you the most In most undisciplined, irreverent and original manner possible. (Richard Feynman)

    Designation: Assistant Professor
    Office: CSE-102   (Ground-Floor)
    Address: Department of Computer Science and Engineering,
    Indian Institute of Technology Kharagpur,
    Paschim Medinipur, West Bengal 721302, INDIA.
    Email: aritrah [at] cse [dot] iitkgp [dot] ac [dot] in
    Phone: +91-3222-304640   (Extn: 84640)
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Institute Page:   http://www.iitkgp.ac.in/department/CS/faculty/cs-aritrah

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