Cyber-attacks

have become increasingly common in recent years. Capable of shutting down nuclear centrifuges, air defense systems, and electrical grids, cyber-attacks pose a serious threat to national security. Hence minimization of information leakage is of paramount interest. In this targeted training, we attempt to bring in one common platform leading experts from international academia and industry, who has produced ingenious attacks and mitigation techniques in this specific domain. The speakers are carefully chosen to cover the thrust areas, ranging from hardware design and machine learning for security to use of focused ion beam based imaging tools for IC counterfeiting and detection of hardware trojan. The audience will be assisted with suitable practical demonstrations to make the learning process more realistic and understandable.

Talks and Abstract

Aritra Hazra
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Title: Formal Verification for CPS Security Assurance
Abstract: The design of unified, efficient, and lightweight cryptographic platform for resource-constrained on-board devices such as sensors, controllers, and actuators in the context of cyber-physical systems (CPS) remains an open and challenging problem, for both academic and industry. Elliptic curve cryptography (ECC) is considered as a promising encryption algorithm for the next generation communications in such devices, as it could provide a strong security level using relatively smaller key size. However, the weakest link for the attackers in such CPS is quite often due to the implementation rather than the mathematical underpinnings. A vast majority of attacks in the recent past have targeted programming flaws and bugs to break security systems. Due to the complexity, empirically verifying such systems is practically impossible, while manual verification as well as testing do not provide adequate guarantees. W study the use of model checking techniques to prove the functional correctness of an elliptic curve cryptography (ECC) library with respect to its formal specification. We demonstrate how the huge state space of the C library can be aptly verified using a hierarchical assume-guarantee verification strategy. Such a formal analysis brings the assurance for security in the usage of ECC algorithms implemented in CPS.
Biography: Dr. Aritra Hazra is currently an Assistant Professor in the Department of Computer Science and Engineering (CSE) at Indian Institute of Technology (IIT) Kharagpur. Earlier, he received the B.E. degree from the Department of CSE, Jadavpur University, Kolkata, India, in 2006, and the M.S. and Ph.D. degrees both from the Department of CSE, IIT Kharagpur, India, in 2010 and 2015, respectively. He has published a book and several research papers in various leading international conferences and journals, including Best Student Papers in VLSI Design Conferences in 2010 and 2017. His current research interests are in formal methods, design verification and VLSI CAD. Dr. Hazra was a recipient of the Microsoft Research (India) Fellowship in 2011, ACM (India) Doctoral Dissertation Award in 2015, IESA Technovation TechnoInventor (PhD) Award in 2015. Dr. Hazra was also awarded with the INAE Young Engineer Award (and became INAE Young Associate) in 2017 and further became the Associate of IASc in 2018. He is a member of IEEE and ACM.

Shivam Bhasin
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Title: One Fault Can Go A Long Way
Abstract: Fault attacks are considered among critical threat to embedded cryptography. This talk will be divided into two parts. The first part of the talk will explore application of faults on advanced security primitives. We present persistent fault analysis introduced at CHES 2017 and its capability to bypass state of the art fault countermeasures as well as higher-order masking with one and only one fault injection. Further, we present novel exploits in lattice based post-quantum cryptographic primitives with one (or few) faults. The second part of the talk will present, to our knowledge, the first practical combined side-channel and differential fault attacks. With application to bit permutation based ciphers like PRESENT and GIFT, practical attacks exploiting laser fault injection with power side-channel will be presented.  
Biography : Shivam Bhasin is a Senior Research Scientist and Programme manager (Cryptographic engineering) Centre for Hardware Assurance in Temasek laboratories, Nanyang Technical University (TL@NTU), Singapore since 2015. His research interests include embedded security, trusted computing and secure designs. He received his PhD from Telecom Paristech in 2011, Master’s from Mines Saint-Etienne, France in 2008. Before NTU, Shivam held position of Research Engineer in Institut Mines-Telecom, France. He was also a visiting researcher at UCL, Belgium (2011) and Kobe University, Japan (2013). Shivam also taught hardware security as an Adjunct Professor in IIT, Kharagpur, India (2018). He regularly publishes at top peer reviewed journals and conferences. Some of his research now also forms a part of ISO/IEC 17825 standard.

Stjepan Picek
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Title: Machine Learning and Implementation Attacks: Perspectives and Pitfalls
Abstract: Recent years showed that machine learning techniques can be a powerful paradigm for implementation attacks, especially profiling side-channel attacks (SCAs). Still, despite all the success, we are limited in our understanding when and how to select appropriate machine learning techniques. Additionally, the results we can obtain are empirical and valid for specific cases where generalization is often difficult. In this talk, we discuss several well-known machine learning techniques, the results obtained, and their limitations. Next, we concentrate on deep learning techniques and potential benefits such techniques can bring to SCA, with an emphasis on real-world scenarios. In the last part of the talk, we discuss how various AI techniques can be used for fault injection attacks.
Biography: Stjepan Picek is an assistant professor in the Cybersecurity group at TU Delft, The Netherlands. His research interests are security/cryptography, machine learning, and evolutionary computation. Prior to the assistant professor position, Stjepan was a postdoctoral researcher at MIT, USA and KU Leuven, Belgium. In July 2015, he completed his PhD at Radboud University Nijmegen, The Netherlands and Faculty of Electrical Engineering and Computing, Zagreb, Croatia. Stjepan also has several years of experience working in industry and government. Up to now, Stjepan gave more than 15 invited talks at conferences and summer schools and published more than 80 refereed papers in journals and conferences.
Stjepan is a member of the organization committee for International Summer School in Cryptography and president of the Croatian IEEE CIS Chapter. He is a general co-chair for Eurocrypt 2020, program committee member and reviewer for a number of conferences and journals, and a member of several professional societies (ACM, IEEE, IACR).

Debojyoti Bhattacharya
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Title: Security testing challenges in automotive systems
Abstract: The number of security vulnerabilities reported in modern day automotive are increasing a lot over past few years. With the advent of connected car and the upcoming plans of autonomous car, impact of such vulnerabilities can have high impact on the safety of the passengers and also on the surrounding. In general automotive companies are looking into security with seriousness. However, security once bolted in, also need to be tested for security in the ecosystem of the car which ranges from chip to cloud. In this talk we will mainly explore the challenges faced by automotive industry to perform security tests in automotive systems.

Soumyajit Dey
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Title: Formal Modeling and Analysis for Safe and Secure CPS
Abstract: We provide an overview of CPS attack scenarios in important domains like automotive and smartgrid. Then we focus on the problem of provably securing a given control loop implementation in the presence of adversarial interventions on data exchange between plant and controller. Such interventions can be thwarted using continuously operating monitoring systems and also cryptographic techniques, both of which consume network and computational resources. We provide a principled approach for intentional skipping of control loop executions which may qualify as a useful control theoretic countermeasure against stealthy attacks which violate message integrity and authenticity. As can be seen, such a control theoretic counter-measure helps in lowering the monitoring/cryptographic security measure overhead and resulting resource consumption. We provide interesting implications of this problem in the context of automotive scheduling.
Biography: Soumyajit Dey joined the dept. of CSE, IIT Kgp in May 2013. He received a B.E. degree in Electronics and Telecommunication Engg. from Jadavpur University, Kolkata in 2004. He received an M.S. followed by PhD degree in Computer Science from Indian Institute of Technology, Kharagpur in 2007 and 2011 respectively. His research interests include 1) Synthesis and Verification of Safe, Secure and Intelligent Cyber Physical Systems, 2) Runtime Systems for Heterogeneous Platforms .

Swarup Bhunia
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Title: Internet of Things Security: The Old and The New
Biography: Swarup Bhunia received the B.E. degree (Hons.) from Jadavpur University, Kolkata, India, in 1995, the M.Tech. degree from IIT Kharagpur, Kharagpur, India, in 1997, and the Ph.D. degree from Purdue University, West Lafayette, IN, USA, in 2005. He was a T. and A. Schroeder Associate Professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He is currently a Professor and a Steven Yatauro Faculty Fellow at the University of Florida, Gainesville, FL, USA. He has authored or coauthored more than 200 publications in peer-reviewed journals and premier conferences. His current research interests include hardware security and trust, adaptive nanocomputing, and novel test methodologies. Dr. Bhunia was a recipient of the IBM Faculty Award in 2013, the National Science Foundation Career Development Award in 2011, the Semiconductor Research Corporation Inventor Recognition Award in 2009, and the SRC Technical Excellence Award in 2005, and several best paper awards/nominations.
He has been serving as an Associate Editor for the IEEE TRANSACTIONS ON CAD, the IEEE TRANSACTIONS ON MULTISCALE COMPUTING SYSTEMS, ACM Journal of Emerging Technologies, and the Journal of Low Power Electronics. He served as a Guest Editor for IEEE Design Test of Computers in 2010 and 2013 and the IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS in 2014. He has served as the Co-Program Chair for the IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the program committee of many IEEE/ACM conferences.


Srivats Ravi
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Title: Security in Automotive 2.0 Era
Biography: Dr. Srivaths Ravi is the Systems and Architecture Manager for C2000 Microcontrollers at Texas Instruments. He currently manages global teams in the C2000 microcontroller product line responsible for developing differentiated system solutions, customer and field engagements, and definition of product strategy and IP/SoC roadmap and specifications. Previously, he was the worldwide silicon development manager for C2000, managing end to end silicon development and delivery as well as sustaining engineering activities.  He has been with TI for 13 years , and is also a senior member of TI’s technical ladder.
Prior to TI, Dr. Ravi was a research staff member with NEC Laboratories America, Princeton. He has worked in the areas of DFT, low power EDA, application-specific processor design, and embedded security. He has over hundred publications in the form of conferences/journal contributions and book chapters, and has received 7 best paper awards and 13 granted patents. He has served on the organizing/program committees of various leading conferences, including as the general chair of VLSI Design Conference 2010, program chair of Asian Test Symposium 2011, program chair of VLSI Test Symposium 2016-17 and general chair of TI Technical Conference in 2018.
Dr. Ravi received the B.Tech degree in Electrical and Electronics Engineering and the Siemens Medal from the Indian Institute of Technology, Madras, India and the M.A. and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, NJ. He is a Senior Member of IEEE.

Debdeep Mukhopadhyay
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Title: Physically Related Functions: A New Primitive for Hardware Security?
Abstract: Lightweight authentication is crucial for end-end security in Cyber Physical Systems. In this talk, we investigate the usage of Physically Unclonable Functions (PUFs) in the context of designing lightweight authentication protocols. Through various versions, we motivate the need of a new primitive called Physically Related Functions, which is based on the principles of PUFs but extends the theory to related challenges. We explain that for any pair of PUFs it is imperative to have challenge subspaces for which the responses are related, and show techniques based on model building of how to efficiently predict such challenge subspaces. Finally, using these primitives we show how to perform node-node authentication without requiring the intervention of any third party trusted server, making the protocols conducive for Cyber Physical Systems.
Biography: Debdeep Mukhopadhyay is currently a full Professor at the Department of Computer Science and Engineering, IIT-Kharagpur, India. 
At IIT Kharagpur he initiated the Secured Embedded Architecture Laboratory (SEAL), with a focus on Embedded Security and Side Channel Attacks (http://cse.iitkgp.ac.in/resgrp/seal/) . Prior to this he worked asAssociate Professor at IIT Kharagpur, visiting scientist at NTU Singapore, a visiting Associate Professor of NYU-Shanghai, Assistant Professor at IIT-Madras, and as Visiting Researcher at NYU Tandon-School-of-Engineering, USA. He holds a PhD, an MS, and a B. Tech from IIT Kharagpur, India. Dr.Mukhopadhyay's research interests are Cryptography, Hardware Security, andVLSI. His books include Fault Tolerant Architectures for Cryptography andHardware Security (Springer), Cryptography and Network Security (Mc GrawHills), Hardware Security: Design, Threats, and Safeguards (CRC Press), andTiming Channels in Cryptography (Springer). He has written more than 150 papersin peer-reviewed conferences and journals and has collaborated with severalIndian and Foreign Organizations. He has been in the program committee of several top International conferences and is an Associate Editor of theInternational Association of Cryptologic Research (IACR) Transactions of CHES,IEEE Transactions on Information Forensics and Security (IEEE TIFS), ACMTransactions on Embedded Computing Systems (ACM-TECS), ACM Journal of Emerging Technologies in Computing Systems (ACM JETC), Journal of Hardware and Systems Security, Journal of Cryptographic Engineering, Springer, He has given several invited talks in industry and academia, including tutorial talks at premier conferences like CHES, WIFS, VLSID. Dr. Mukhopadhyay is the recipient of the prestigious Swarnajayanti DST Fellowship 2015-16, Data Security Council of India Award for Cyber Security Education, Young Scientist award from the Indian National Science Academy, the Young Engineer award from the Indian National Academy of Engineers, and is a Young Associate of the Indian Academy of Science. He was also awarded the Outstanding Young Faculty fellowship in 2011 from IIT Kharagpur, and the Techno-Inventor Best PhD award by the IndianSemiconductor Association. He has recently incubated a start-up on HardwareSecurity, ESP Pvt Ltd at IIT Kharagpur (http://esp-research.com/). In the context of block chains, he is pursuing research to realize an end-end secure supply chain flow for Integrated Circuits (IC), using the concept of Physically Unclonable Functions (PUFs).

Jeevan Visvesha
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Title: Connected car is under attack.
Abstract: Eye catching to the Automotive world and highlighting read world use cases because of lack of hardware security Loopholes, attack surfaces and impacts in the V2I Communication and in TCU Some of good practices around hardware security to mitigate such attacks.
Biography: Jeevan Visvesha is a Hardware and Automotive Security Lead at OLA Electric Mobility Private Limited, having experience across domains like Automotive, hardware, IOT, product security etc. Previously he was working in Robert Bosch. He is involved in providing hardware security requirements to the company and also owns the responsibilities of a hardware pentesting. He believes and implements Secure concepts throughout the life-cycle from requirement to deployment.

Manaar Alam
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Title: In-situ Extraction of Randomness from Computer Architecture
Abstract: True Random Number Generators (TRNGs) are one of the most crucial components in the design and use of cryptographic protocols and communication. Predictability of such random numbers are catastrophic and can lead to the complete collapse of security, as all the mathematical proofs are based on the entropy of the source which generates these bit patterns. The randomness in the TRNGs is hugely attributed to the inherent noise of the system, which is often derived from hardware subsystems operating in an ambiguous manner. However, most of these solutions need an add-on device to provide these randomness sources, which can lead to not only latency issues but also can be a potential target of adversaries by probing such an interface. In this talk, we will see how to alleviate these issues by proposing an in-situ TRNG construction, which depends on the functioning of the underlying hardware architecture. These functions are observed via the Hardware Performance Counters (HPCs) and are shown to exhibit high-quality randomness in the least significant bit positions. We provide extensive experiments to research on the choice of the HPCs, and their ability to pass the standard NIST and AIS 20/31 Tests. We also analyze a possible scenario where an adversary tries to interfere with the HPC values and show its effect on the TRNG output with respect to the NIST and AIS 20/31 Tests. Additionally, to alleviate the delay caused for accessing the HPC events and increase the throughput of the random-source, we also propose a methodology to cascade the random numbers from the HPC values with a secured hash function.
Biography: Manaar is a PhD scholar at IIT Kharagpur in the Dept. of CSE. He is currently working under the supervision of Prof. Debdeep Mukhopadhyay. He obtained an M. Tech. degree from the Dept. of CSE at IIT Dhanbad in 2016 and obtained a B. Tech. degree from the Dept. of CSE at IEM Kolkata under WBUT in 2013. He is a member of the Secured Embedded Architecture Laboratory and his primary research interests mainly include Application of Machine Learning in the field of Hardware and Software Security, particularly designing of robust machine learning based countermeasure for detecting Side-Channel Attacks, Malwares, Ransomwares etc. He also has interest in exploiting side-channel leakages from micro-architectural events to mount side-channel attacks. His other research interests include designing of fault resistant robust machine learning, exploring machine learning attack resistance of Physically Unclonable Functions (PUFs), and anything conjoining Machine Learning and Security. He has been a Visiting Research Assistant in the School of Computer Science and Engineering at NTU Singapore from August 2017 to January 2018, where he worked with Dr. Thambipillai Srikanthan and Dr. Siew-Kei Lam. He obtained prestigious IBM PhD Fellowship in 2019.

Hands-On (10th December)
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The objective of this tutorial is to demonstrate the feasibility of Side-Channel Attacks (SCA) on low-cost commercial FPGA development boards. FPGA development boards targeted for side-channel evaluation are costly and may require specific operating procedures. This hands-on tutorial aims to provide the participants with a practical experience of power side-channel analysis on AES (using correlation power analysis or CPA) implemented on low-cost commercial FPGA boards. This tutorial includes a brief introduction to CPA on AES and a short demonstration on trace acquisition from Digilent Basys 3 FPGA board. Participants would engage in implementing CPA attack on AES using power traces acquired from Basys 3 FPGA board to recover the partial encryption key.


Hands-On (11th December)
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In this session, we demonstrate the evaluation of key performance metrics of Physically Unclonable Functions: Uniqueness, Uniformity and Reliability using the data collected in the Lab demonstration. We also discuss machine learning resistance of PUFs, followed by an analysis of two PUF circuits and their modelling results.